mihir8181 / VerilogHDL-Codes Star 41 Code Issues Pull requests Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results. counterfsmasynchronousverilogfifotestbenchesverilog-hdlverilog-programsmealy-machine-codemoore-machine-codeverilog-projectfifo-bufferverilog-coden-bit-aluverilogvalidationdesign-under-testasynchronous-fifofifo-verilog Updated May 10, 2019Verilog
YajanaRao / Verilog Star 2 Code Issues Pull requests Verilog Programsfsmstate-machinefunctionstasksdata-flowverilogmuxisebehavioralhdlverilog-hdlvending-machinestructuralmoore-machineverilog-programsmealy-machine-codemoore-machine-codeverilog-projectflipflopverilog-code Updated Apr 16, 2021Verilog
BaseMax / MealyMachines Sponsor Star 2 Code Issues Pull requests This repository contains a collection of Mealy machine implementations in PHP for performing various arithmetic operations.phpmealy-machinemealymealy-machine-codemealy-machinesmealy-phpphp-mealyphp-mealy-machinemealy-machine-php Updated Jul 14, 2023PHP
MuballighHossain / Mealy_Machine_VLSI Star 1 Code Issues Pull requests verilogvlsimealy-machinemealymealy-machine-code Updated Aug 20, 2022Verilog
rasitekrem / MealyMachine Star 0 Code Issues Pull requests Mealy Machine with Javascriptjavascriptstate-machinefinite-state-machinemealy-machineautomata-theorymealyautomata-mealymealy-with-javascriptmealy-machine-code Updated Dec 2, 2017JavaScript
mariateodorapopescu / numerical_computers1_labs Star 0 Code Issues Pull requests Here are some of my numerical computers1 laboratory assignments that I had in 2nd yearfsmprojectassignmentveriloguninumerical-computationmealy-machinemoore-machinemooremealy-machine-codeuniverityuni-projectmealy-fsm Updated Feb 12, 2024Tcl
VoonnaSampath / Verilog-Digital-Circuits Star 0 Code Issues Pull requests Verilog code for combinational and sequential circuits verilogbcdmuxhdlmultiplexerverilog-hdlmoore-machineaddersmealy-machine-codeflipfloplatchessynchronous-countersequentialcircuitsshift-registers7segmentdisplaydigitalcircuitsflipflop-codessubtractors Updated Dec 2, 2025Verilog