SimoneDeidier / RL-PROJECT-2023 Star 2 Code Issues Pull requests Final project of Logical Networks course - Politecnico di Milano 2022/23fsmhardwarevhdlfinite-state-machinexilinxvivadodatapathdigital-logiclogic-gatestestbenchdigital-designrtl-designhardware-designlogic-networksmemory-interface Updated Apr 8, 2026VHDL
scwpark / MQM-Wave-based-Computing-ALU-and-Data-Transfer Star 0 Code Issues Pull requests MQM Wave-based computing/ALU (CPU/GPU/NPU) and Data Transfer Systems for Optics and HBM(Prior Art, 2026.03.04)pamsignal-processinghbmofdmmemory-bandwidthdata-transmissionmulti-carrierfrequency-encodingparallel-transmissionfrequency-multiplexingmemory-interfacemulti-bit-modulationmultilevel-signalvoltage-based-modulationsuperposition-codinghigh-speed-linkdie-to-die-communicationnextgenaluwave-based-aluwave-based-computing Updated Apr 23, 2026
Francesco-Barillari / Differential-Filter-on-Memory-VHDL- Star 0 Code Issues Pull requests VHDL implementation of a memory-mapped differential filter controlled by an FSM.vhdlfinite-state-machinehardware-designmemory-interface Updated Dec 31, 2025VHDL