riscv-verification

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Rivoryxa-Technologies / formal-fsm-verification

Formal verification reference flow: an FSM safety property proven unbounded by k-induction with SymbiYosys, Yosys, and z3. The same toolchain we use to prove coverage holes unreachable on real cores.

fsm hardware verification riscv rtl z3 model-checking systemverilog formal-verification k-induction yosys sva symbiyosys coverage-closure riscv-verification

Updated Sep 17, 2026
SystemVerilog

Rivoryxa-Technologies / uvm-alu-testbench

Star

UVM 1.2 reference environment for a pipelined ALU: agent, driver, monitor, scoreboard with reference model, and functional coverage. Lints clean under Verilator.

coverage hardware verification rtl systemverilog uvm testbench verilator functional-verification riscv-verification

Updated Sep 17, 2026
SystemVerilog

Rivoryxa-Technologies / Rivoryxa-Technologies

Star

Rivoryxa Technologies: RISC-V and RTL verification. Formal proofs, bug reproduction, coverage closure, and ACT4 compliance testing on open-source tools.

verification riscv formal-verification riscv-verification

Updated Sep 17, 2026

Rivoryxa-Technologies / riscv-sva-library

Star

Reusable SystemVerilog assertion (SVA) checkers for handshakes, FIFOs, one-hot buses, and CDC synchronizers. Bind into RTL for simulation or hand to a formal engine.

hardware verification assertions riscv rtl bind systemverilog formal-verification sva assertion-based-verification riscv-verification

Updated Sep 17, 2026
SystemVerilog

Rivoryxa-Technologies / cocotb-alu-verification

Star

Python verification reference flow: cocotb 2.x testbench with a reference model, directed and constrained-random tests, and functional coverage. Verified on Icarus Verilog.

python hardware verification regression rtl verilog icarus-verilog testbench functional-verification cocotb riscv-verification verification-automation

Updated Sep 17, 2026
Python

Rivoryxa-Technologies / cdc-verification

Star

Clock-domain-crossing verification: a dual-clock asynchronous FIFO with Gray pointers and 2-flop synchronizers, checked across two independent clocks with cocotb. Verified on Icarus Verilog.

python hardware verification rtl synchronizer systemverilog cdc verilator metastability clock-domain-crossing cocotb async-fifo riscv-verification

Updated Sep 17, 2026
Python

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