gws8820 / RISCV-CPU Star 9 Code Issues Pull requests A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)cpufpgaruntimearchitectureriscvveriloguartsystemveriloghdlmicroarchitecturebranch-predictioncoremarkrv32icpu-architecturedhrystonerv32imuart-programming Updated Aug 2, 2026HTML
ben5en / MSP430_UartMonitor Star 1 Code Issues Pull requests This project shows the possibility to view and change variables via a serial interface (UART) during the program runtime.debuggerdebuggingserialmsp430uartprogramtexas-instrumentsuart-protocoltexasinstrumentsuart-interfaceuart-debugginguart-monitormsp430fr2433programmodeluartuart-programming Updated Sep 6, 2019Batchfile