Computer Engineering student at the Technion and Cornell Engineering, focused on digital design, ASICs, FPGAs, embedded systems, and hardware/software co-design.
I enjoy taking hardware from RTL through verification, FPGA prototyping, and physical implementation. My recent work includes two hardened SKY130 Tiny Tapeout game designs and a SystemVerilog VGA arcade game running on a DE10-Standard FPGA.
| Project | Highlights |
|---|---|
| JA Achtung Full — 1x2 Tiny Tapeout design | A two-player hardware game with 64-direction movement, a 2-bit QSPI PSRAM framebuffer, dual gamepads, and direct 640×480 VGA. Verified against Python reference models through RTL, gate-level, and RTL-to-GDS checks. |
| FPGA VGA Arcade Game | A Pokémon-inspired arcade game implemented in SystemVerilog for the Terasic DE10-Standard, including hardware sprite composition, collision detection, PS/2 input, and audio. |
| JA Achtung Compact — 1x1 Tiny Tapeout design | An area-optimized one-tile version using a 1-bit QSPI PSRAM framebuffer, direct VGA, and the same hardware/software co-verification approach. |
| WeStream | A Zoom-style screen, voice, and text streaming platform built from scratch in Python over raw TCP sockets as my 2020 high-school final project. |
Project presentation · Final project report
SystemVerilog · Verilog · FPGA · ASIC · SKY130 · Tiny Tapeout · cocotb · LibreLane · VGA · PSRAM · Python