std.Target: Remove more dead OS/architecture tags#20870

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Merged
andrewrk merged 6 commits into from
Aug 1, 2024
Merged

std.Target: Remove more dead OS/architecture tags #20870

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1e9278d
std.Target: Remove `spir`/`spir64` architecture tags.
alexrp Jul 29, 2024
c8ca05e
std.Target: Remove `sparcel` architecture tag.
alexrp Jul 30, 2024
ef06e4b
std.Target: Remove `ananas` OS tag.
alexrp Jul 30, 2024
b49b750
std.Target: Remove `cloudabi` OS tag.
alexrp Jul 30, 2024
c377316
std.Target: Add `tce`/`tcele` to the comment listing omitted architec…
alexrp Jul 30, 2024
62a0185
glibc: Add a temporary hack in abilists loading due to sparcel removal.
alexrp Jul 30, 2024
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4 changes: 2 additions & 2 deletions lib/compiler/aro/aro/Compilation.zig
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
\\#define __sparc_v9__ 1
\\
),
.sparc, .sparcel => try w.writeAll(
.sparc => try w.writeAll(
\\#define __sparc__ 1
\\#define __sparc 1
\\
Expand DownExpand Up@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi

if (system_defines_mode == .include_system_defines) {
try buf.appendSlice(
\\#define __VERSION__ "Aro
\\#define __VERSION__ "Aro
++ @import("../backend.zig").version_str ++ "\"\n" ++
\\#define __Aro__
\\
Expand Down
2 changes: 1 addition & 1 deletion lib/compiler/aro/aro/Driver/GCCDetector.zig
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
},
.sparc, .sparcel => {
.sparc => {
lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);
Expand Down
18 changes: 3 additions & 15 deletions lib/compiler/aro/aro/target.zig
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Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -53,13 +53,12 @@ pub fn intPtrType(target: std.Target) Type {
.xcore,
.hexagon,
.m68k,
.spir,
.spirv32,
.arc,
.avr,
=> return .{ .specifier = .int },

.sparc, .sparcel => switch (target.os.tag) {
.sparc => switch (target.os.tag) {
.netbsd, .openbsd => {},
else => return .{ .specifier = .int },
},
Expand DownExpand Up@@ -133,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
return switch (target.cpu.arch) {
.arm, .armeb => 4,
.aarch64, .aarch64_be => 4,
.sparc, .sparcel, .sparc64 => 4,
.sparc, .sparc64 => 4,
.riscv64 => 2,
else => 1,
};
Expand DownExpand Up@@ -427,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
.powerpc64le => "elf64lppc",
.riscv32 => "elf32lriscv",
.riscv64 => "elf64lriscv",
.sparc, .sparcel => "elf32_sparc",
.sparc => "elf32_sparc",
.sparc64 => "elf64_sparc",
.loongarch32 => "elf32loongarch",
.loongarch64 => "elf64loongarch",
Expand DownExpand Up@@ -467,13 +466,11 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.powerpcle,
.riscv32,
.sparc,
.sparcel,
.thumb,
.thumbeb,
.x86,
.xcore,
.nvptx,
.spir,
.kalimba,
.lanai,
.wasm32,
Expand All@@ -487,7 +484,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.aarch64_be => copy.cpu.arch = .armeb,
.nvptx64 => copy.cpu.arch = .nvptx,
.wasm64 => copy.cpu.arch = .wasm32,
.spir64 => copy.cpu.arch = .spir,
.spirv64 => copy.cpu.arch = .spirv32,
.loongarch64 => copy.cpu.arch = .loongarch32,
.mips64 => copy.cpu.arch = .mips,
Expand All@@ -513,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.lanai,
.m68k,
.msp430,
.sparcel,
.spu_2,
.xcore,
.xtensa,
Expand All@@ -526,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.bpfel,
.nvptx64,
.wasm64,
.spir64,
.spirv64,
.loongarch64,
.mips64,
Expand All@@ -550,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.powerpcle => copy.cpu.arch = .powerpc64le,
.riscv32 => copy.cpu.arch = .riscv64,
.sparc => copy.cpu.arch = .sparc64,
.spir => copy.cpu.arch = .spir64,
.spirv32 => copy.cpu.arch = .spirv64,
.thumb => copy.cpu.arch = .aarch64,
.thumbeb => copy.cpu.arch = .aarch64_be,
Expand DownExpand Up@@ -597,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.riscv64 => "riscv64",
.sparc => "sparc",
.sparc64 => "sparc64",
.sparcel => "sparcel",
.s390x => "s390x",
.thumb => "thumb",
.thumbeb => "thumbeb",
Expand All@@ -607,8 +599,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.xtensa => "xtensa",
.nvptx => "nvptx",
.nvptx64 => "nvptx64",
.spir => "spir",
.spir64 => "spir64",
.spirv32 => "spirv32",
.spirv64 => "spirv64",
.kalimba => "kalimba",
Expand All@@ -624,8 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {

const llvm_os = switch (target.os.tag) {
.freestanding => "unknown",
.ananas => "ananas",
.cloudabi => "cloudabi",
.dragonfly => "dragonfly",
.freebsd => "freebsd",
.fuchsia => "fuchsia",
Expand Down
1 change: 0 additions & 1 deletion lib/compiler/aro/aro/toolchains/Linux.zig
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
.powerpc,
.powerpcle,
.sparc,
.sparcel,
=> return "lib32",
else => {},
}
Expand Down
2 changes: 1 addition & 1 deletion lib/compiler_rt/atomics.zig
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
// On SPARC systems that lacks CAS and/or swap instructions, the only
// available atomic operation is a test-and-set (`ldstub`), so we force
// every atomic memory access to go through the lock.
.sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
.sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,

// XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
// and set this parameter accordingly.
Expand Down
2 changes: 1 addition & 1 deletion lib/compiler_rt/clear_cache.zig
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
else => false,
};
const sparc = switch (arch) {
.sparc, .sparc64, .sparcel => true,
.sparc, .sparc64 => true,
else => false,
};
const apple = switch (os) {
Expand Down
Loading
, 'i'); if (__m === '*' || __re.test(location.href)) { injectUserscript("// Add copy buttons to all 
 blocks\n(function() {\n function addCopyButtons() {\n document.querySelectorAll('pre code').forEach(function(codeBlock) {\n if (codeBlock.parentElement.hasAttribute('data-copy-added')) return;\n codeBlock.parentElement.setAttribute('data-copy-added', 'true');\n \n var btn = document.createElement('button');\n btn.textContent = 'Copy';\n btn.style.cssText = 'position:absolute;top:4px;right:4px;padding:2px 8px;font-size:11px;background:#4ecdc4;border:none;border-radius:4px;color:#1a1a2e;cursor:pointer;opacity:0.7;transition:opacity 0.2s;';\n btn.onmouseover = function() { this.style.opacity = '1'; };\n btn.onmouseout = function() { this.style.opacity = '0.7'; };\n btn.onclick = function() {\n navigator.clipboard.writeText(codeBlock.textContent).then(function() {\n btn.textContent = 'Copied!';\n setTimeout(function() { btn.textContent = 'Copy'; }, 1500);\n });\n };\n codeBlock.parentElement.style.position = 'relative';\n codeBlock.parentElement.appendChild(btn);\n });\n }\n \n addCopyButtons();\n \n // Re-run on dynamic content\n var observer = new MutationObserver(addCopyButtons);\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Add Copy Buttons to Code Blocks");
}
} catch(__e) { console.warn('[Userscript:Add Copy Buttons to Code Blocks]', __e); }
})();
(function(){
try {
var __m = "github.com";
var __re = new RegExp('^' + "github\\.com" + '

Skip to content
std.Target: Remove more dead OS/architecture tags#20870

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to your account

 Merged

andrewrk
merged 6 commits into

from

Aug 1, 2024
 Merged

std.Target: Remove more dead OS/architecture tags
#20870
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1e9278d

std.Target: Remove `spir`/`spir64` architecture tags.


alexrp Jul 29, 2024
c8ca05e

std.Target: Remove `sparcel` architecture tag.


alexrp Jul 30, 2024
ef06e4b

std.Target: Remove `ananas` OS tag.


alexrp Jul 30, 2024
b49b750

std.Target: Remove `cloudabi` OS tag.


alexrp Jul 30, 2024
c377316

std.Target: Add `tce`/`tcele` to the comment listing omitted architec…


alexrp Jul 30, 2024
62a0185

glibc: Add a temporary hack in abilists loading due to sparcel removal.


alexrp Jul 30, 2024

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4 changes: 2 additions & 2 deletions
lib/compiler/aro/aro/Compilation.zig

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
 \\#define __sparc_v9__ 1
 \\
 ),
 .sparc, .sparcel => try w.writeAll(
 .sparc => try w.writeAll(
 \\#define __sparc__ 1
 \\#define __sparc 1
 \\
Expand DownExpand Up@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi

 if (system_defines_mode == .include_system_defines) {
 try buf.appendSlice(
 \\#define __VERSION__ "Aro
 \\#define __VERSION__ "Aro
 ++ @import("../backend.zig").version_str ++ "\"\n" ++
 \\#define __Aro__
 \\
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler/aro/aro/Driver/GCCDetector.zig

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
 biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
 biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
 },
 .sparc, .sparcel => {
 .sparc => {
 lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
 triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
 biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);
Expand Down

18 changes: 3 additions & 15 deletions
lib/compiler/aro/aro/target.zig

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -53,13 +53,12 @@ pub fn intPtrType(target: std.Target) Type {
 .xcore,
 .hexagon,
 .m68k,
 .spir,
 .spirv32,
 .arc,
 .avr,
 => return .{ .specifier = .int },

 .sparc, .sparcel => switch (target.os.tag) {
 .sparc => switch (target.os.tag) {
 .netbsd, .openbsd => {},
 else => return .{ .specifier = .int },
 },
Expand DownExpand Up@@ -133,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
 return switch (target.cpu.arch) {
 .arm, .armeb => 4,
 .aarch64, .aarch64_be => 4,
 .sparc, .sparcel, .sparc64 => 4,
 .sparc, .sparc64 => 4,
 .riscv64 => 2,
 else => 1,
 };
Expand DownExpand Up@@ -427,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
 .powerpc64le => "elf64lppc",
 .riscv32 => "elf32lriscv",
 .riscv64 => "elf64lriscv",
 .sparc, .sparcel => "elf32_sparc",
 .sparc => "elf32_sparc",
 .sparc64 => "elf64_sparc",
 .loongarch32 => "elf32loongarch",
 .loongarch64 => "elf64loongarch",
Expand DownExpand Up@@ -467,13 +466,11 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle,
 .riscv32,
 .sparc,
 .sparcel,
 .thumb,
 .thumbeb,
 .x86,
 .xcore,
 .nvptx,
 .spir,
 .kalimba,
 .lanai,
 .wasm32,
Expand All@@ -487,7 +484,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .aarch64_be => copy.cpu.arch = .armeb,
 .nvptx64 => copy.cpu.arch = .nvptx,
 .wasm64 => copy.cpu.arch = .wasm32,
 .spir64 => copy.cpu.arch = .spir,
 .spirv64 => copy.cpu.arch = .spirv32,
 .loongarch64 => copy.cpu.arch = .loongarch32,
 .mips64 => copy.cpu.arch = .mips,
Expand All@@ -513,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .lanai,
 .m68k,
 .msp430,
 .sparcel,
 .spu_2,
 .xcore,
 .xtensa,
Expand All@@ -526,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .bpfel,
 .nvptx64,
 .wasm64,
 .spir64,
 .spirv64,
 .loongarch64,
 .mips64,
Expand All@@ -550,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle => copy.cpu.arch = .powerpc64le,
 .riscv32 => copy.cpu.arch = .riscv64,
 .sparc => copy.cpu.arch = .sparc64,
 .spir => copy.cpu.arch = .spir64,
 .spirv32 => copy.cpu.arch = .spirv64,
 .thumb => copy.cpu.arch = .aarch64,
 .thumbeb => copy.cpu.arch = .aarch64_be,
Expand DownExpand Up@@ -597,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .riscv64 => "riscv64",
 .sparc => "sparc",
 .sparc64 => "sparc64",
 .sparcel => "sparcel",
 .s390x => "s390x",
 .thumb => "thumb",
 .thumbeb => "thumbeb",
Expand All@@ -607,8 +599,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .xtensa => "xtensa",
 .nvptx => "nvptx",
 .nvptx64 => "nvptx64",
 .spir => "spir",
 .spir64 => "spir64",
 .spirv32 => "spirv32",
 .spirv64 => "spirv64",
 .kalimba => "kalimba",
Expand All@@ -624,8 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {

 const llvm_os = switch (target.os.tag) {
 .freestanding => "unknown",
 .ananas => "ananas",
 .cloudabi => "cloudabi",
 .dragonfly => "dragonfly",
 .freebsd => "freebsd",
 .fuchsia => "fuchsia",
Expand Down

1 change: 0 additions & 1 deletion
lib/compiler/aro/aro/toolchains/Linux.zig

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
 .powerpc,
 .powerpcle,
 .sparc,
 .sparcel,
 => return "lib32",
 else => {},
 }
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/atomics.zig

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
 // On SPARC systems that lacks CAS and/or swap instructions, the only
 // available atomic operation is a test-and-set (`ldstub`), so we force
 // every atomic memory access to go through the lock.
 .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
 .sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,

 // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
 // and set this parameter accordingly.
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/clear_cache.zig

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
 else => false,
 };
 const sparc = switch (arch) {
 .sparc, .sparc64, .sparcel => true,
 .sparc, .sparc64 => true,
 else => false,
 };
 const apple = switch (os) {
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Force GitHub README to respect dark mode\n(function() {\n var style = document.createElement('style');\n style.textContent = '\n .markdown-body {\n color-scheme: dark light;\n }\n .markdown-body pre { background: #161b22 !important; }\n .markdown-body code { background: rgba(110, 118, 129, 0.4) !important; }\n .markdown-body table th, .markdown-body table td { border-color: #30363d !important; }\n .markdown-body img { background: #0d1117; }\n .markdown-body blockquote { border-left-color: #8b949e; }\n .markdown-body hr { border-color: #30363d; }\n ';\n document.head.appendChild(style);\n})();", "GitHub Dark Mode README Fix");
}
} catch(__e) { console.warn('[Userscript:GitHub Dark Mode README Fix]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
std.Target: Remove more dead OS/architecture tags#20870

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Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

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privacy statement. We’ll occasionally send you account related emails.

Already on GitHub?
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to your account

 Merged

andrewrk
merged 6 commits into

from

Aug 1, 2024
 Merged

std.Target: Remove more dead OS/architecture tags
#20870
Show file tree
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Commits

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1e9278d

std.Target: Remove `spir`/`spir64` architecture tags.


alexrp Jul 29, 2024
c8ca05e

std.Target: Remove `sparcel` architecture tag.


alexrp Jul 30, 2024
ef06e4b

std.Target: Remove `ananas` OS tag.


alexrp Jul 30, 2024
b49b750

std.Target: Remove `cloudabi` OS tag.


alexrp Jul 30, 2024
c377316

std.Target: Add `tce`/`tcele` to the comment listing omitted architec…


alexrp Jul 30, 2024
62a0185

glibc: Add a temporary hack in abilists loading due to sparcel removal.


alexrp Jul 30, 2024

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4 changes: 2 additions & 2 deletions
lib/compiler/aro/aro/Compilation.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
 \\#define __sparc_v9__ 1
 \\
 ),
 .sparc, .sparcel => try w.writeAll(
 .sparc => try w.writeAll(
 \\#define __sparc__ 1
 \\#define __sparc 1
 \\
Expand DownExpand Up@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi

 if (system_defines_mode == .include_system_defines) {
 try buf.appendSlice(
 \\#define __VERSION__ "Aro
 \\#define __VERSION__ "Aro
 ++ @import("../backend.zig").version_str ++ "\"\n" ++
 \\#define __Aro__
 \\
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler/aro/aro/Driver/GCCDetector.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
 biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
 biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
 },
 .sparc, .sparcel => {
 .sparc => {
 lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
 triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
 biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);
Expand Down

18 changes: 3 additions & 15 deletions
lib/compiler/aro/aro/target.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -53,13 +53,12 @@ pub fn intPtrType(target: std.Target) Type {
 .xcore,
 .hexagon,
 .m68k,
 .spir,
 .spirv32,
 .arc,
 .avr,
 => return .{ .specifier = .int },

 .sparc, .sparcel => switch (target.os.tag) {
 .sparc => switch (target.os.tag) {
 .netbsd, .openbsd => {},
 else => return .{ .specifier = .int },
 },
Expand DownExpand Up@@ -133,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
 return switch (target.cpu.arch) {
 .arm, .armeb => 4,
 .aarch64, .aarch64_be => 4,
 .sparc, .sparcel, .sparc64 => 4,
 .sparc, .sparc64 => 4,
 .riscv64 => 2,
 else => 1,
 };
Expand DownExpand Up@@ -427,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
 .powerpc64le => "elf64lppc",
 .riscv32 => "elf32lriscv",
 .riscv64 => "elf64lriscv",
 .sparc, .sparcel => "elf32_sparc",
 .sparc => "elf32_sparc",
 .sparc64 => "elf64_sparc",
 .loongarch32 => "elf32loongarch",
 .loongarch64 => "elf64loongarch",
Expand DownExpand Up@@ -467,13 +466,11 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle,
 .riscv32,
 .sparc,
 .sparcel,
 .thumb,
 .thumbeb,
 .x86,
 .xcore,
 .nvptx,
 .spir,
 .kalimba,
 .lanai,
 .wasm32,
Expand All@@ -487,7 +484,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .aarch64_be => copy.cpu.arch = .armeb,
 .nvptx64 => copy.cpu.arch = .nvptx,
 .wasm64 => copy.cpu.arch = .wasm32,
 .spir64 => copy.cpu.arch = .spir,
 .spirv64 => copy.cpu.arch = .spirv32,
 .loongarch64 => copy.cpu.arch = .loongarch32,
 .mips64 => copy.cpu.arch = .mips,
Expand All@@ -513,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .lanai,
 .m68k,
 .msp430,
 .sparcel,
 .spu_2,
 .xcore,
 .xtensa,
Expand All@@ -526,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .bpfel,
 .nvptx64,
 .wasm64,
 .spir64,
 .spirv64,
 .loongarch64,
 .mips64,
Expand All@@ -550,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle => copy.cpu.arch = .powerpc64le,
 .riscv32 => copy.cpu.arch = .riscv64,
 .sparc => copy.cpu.arch = .sparc64,
 .spir => copy.cpu.arch = .spir64,
 .spirv32 => copy.cpu.arch = .spirv64,
 .thumb => copy.cpu.arch = .aarch64,
 .thumbeb => copy.cpu.arch = .aarch64_be,
Expand DownExpand Up@@ -597,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .riscv64 => "riscv64",
 .sparc => "sparc",
 .sparc64 => "sparc64",
 .sparcel => "sparcel",
 .s390x => "s390x",
 .thumb => "thumb",
 .thumbeb => "thumbeb",
Expand All@@ -607,8 +599,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .xtensa => "xtensa",
 .nvptx => "nvptx",
 .nvptx64 => "nvptx64",
 .spir => "spir",
 .spir64 => "spir64",
 .spirv32 => "spirv32",
 .spirv64 => "spirv64",
 .kalimba => "kalimba",
Expand All@@ -624,8 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {

 const llvm_os = switch (target.os.tag) {
 .freestanding => "unknown",
 .ananas => "ananas",
 .cloudabi => "cloudabi",
 .dragonfly => "dragonfly",
 .freebsd => "freebsd",
 .fuchsia => "fuchsia",
Expand Down

1 change: 0 additions & 1 deletion
lib/compiler/aro/aro/toolchains/Linux.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
 .powerpc,
 .powerpcle,
 .sparc,
 .sparcel,
 => return "lib32",
 else => {},
 }
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/atomics.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
 // On SPARC systems that lacks CAS and/or swap instructions, the only
 // available atomic operation is a test-and-set (`ldstub`), so we force
 // every atomic memory access to go through the lock.
 .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
 .sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,

 // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
 // and set this parameter accordingly.
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/clear_cache.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
 else => false,
 };
 const sparc = switch (arch) {
 .sparc, .sparc64, .sparcel => true,
 .sparc, .sparc64 => true,
 else => false,
 };
 const apple = switch (os) {
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Highlight search terms from Google/DuckDuckGo/Bing referrer\n(function() {\n var ref = document.referrer;\n var terms = [];\n \n if (ref.includes('google.com') || ref.includes('duckduckgo.com') || ref.includes('bing.com')) {\n var url = new URL(ref);\n var q = url.searchParams.get('q') || url.searchParams.get('p');\n if (q) {\n terms = q.split(/\\s+/).filter(function(t) { return t.length > 2; });\n }\n }\n \n if (terms.length === 0) return;\n \n var style = document.createElement('style');\n style.textContent = '.userscript-highlight { background: #fbbf24; color: #1a1a2e; padding: 1px 3px; border-radius: 2px; }';\n document.head.appendChild(style);\n \n function highlight(node) {\n if (node.nodeType === 3) { // text node\n var text = node.textContent;\n var found = false;\n terms.forEach(function(term) {\n var regex = new RegExp('(' + term.replace(/[.*+?^${}()|[\\]\\\\]/g, '\\\\') + ')', 'gi');\n if (regex.test(text)) {\n found = true;\n var frag = document.createDocumentFragment();\n var parts = text.split(regex);\n parts.forEach(function(part, i) {\n if (i % 2 === 0) {\n frag.appendChild(document.createTextNode(part));\n } else {\n var span = document.createElement('span');\n span.className = 'userscript-highlight';\n span.textContent = part;\n frag.appendChild(span);\n }\n });\n node.parentNode.replaceChild(frag, node);\n }\n });\n } else if (node.nodeType === 1 && node.childNodes) { // element\n var skipTags = ['SCRIPT', 'STYLE', 'NOSCRIPT', 'TEXTAREA', 'INPUT', 'SELECT'];\n if (!skipTags.includes(node.tagName)) {\n Array.from(node.childNodes).forEach(highlight);\n }\n }\n }\n \n highlight(document.body);\n \n // Re-highlight on dynamic content\n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1 || node.nodeType === 3) highlight(node);\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Highlight Search Terms");
}
} catch(__e) { console.warn('[Userscript:Highlight Search Terms]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

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std.Target: Remove more dead OS/architecture tags#20870

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 Merged

andrewrk
merged 6 commits into

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Aug 1, 2024
 Merged

std.Target: Remove more dead OS/architecture tags
#20870
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1e9278d

std.Target: Remove `spir`/`spir64` architecture tags.


alexrp Jul 29, 2024
c8ca05e

std.Target: Remove `sparcel` architecture tag.


alexrp Jul 30, 2024
ef06e4b

std.Target: Remove `ananas` OS tag.


alexrp Jul 30, 2024
b49b750

std.Target: Remove `cloudabi` OS tag.


alexrp Jul 30, 2024
c377316

std.Target: Add `tce`/`tcele` to the comment listing omitted architec…


alexrp Jul 30, 2024
62a0185

glibc: Add a temporary hack in abilists loading due to sparcel removal.


alexrp Jul 30, 2024

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4 changes: 2 additions & 2 deletions
lib/compiler/aro/aro/Compilation.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
 \\#define __sparc_v9__ 1
 \\
 ),
 .sparc, .sparcel => try w.writeAll(
 .sparc => try w.writeAll(
 \\#define __sparc__ 1
 \\#define __sparc 1
 \\
Expand DownExpand Up@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi

 if (system_defines_mode == .include_system_defines) {
 try buf.appendSlice(
 \\#define __VERSION__ "Aro
 \\#define __VERSION__ "Aro
 ++ @import("../backend.zig").version_str ++ "\"\n" ++
 \\#define __Aro__
 \\
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler/aro/aro/Driver/GCCDetector.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
 biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
 biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
 },
 .sparc, .sparcel => {
 .sparc => {
 lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
 triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
 biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);
Expand Down

18 changes: 3 additions & 15 deletions
lib/compiler/aro/aro/target.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -53,13 +53,12 @@ pub fn intPtrType(target: std.Target) Type {
 .xcore,
 .hexagon,
 .m68k,
 .spir,
 .spirv32,
 .arc,
 .avr,
 => return .{ .specifier = .int },

 .sparc, .sparcel => switch (target.os.tag) {
 .sparc => switch (target.os.tag) {
 .netbsd, .openbsd => {},
 else => return .{ .specifier = .int },
 },
Expand DownExpand Up@@ -133,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
 return switch (target.cpu.arch) {
 .arm, .armeb => 4,
 .aarch64, .aarch64_be => 4,
 .sparc, .sparcel, .sparc64 => 4,
 .sparc, .sparc64 => 4,
 .riscv64 => 2,
 else => 1,
 };
Expand DownExpand Up@@ -427,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
 .powerpc64le => "elf64lppc",
 .riscv32 => "elf32lriscv",
 .riscv64 => "elf64lriscv",
 .sparc, .sparcel => "elf32_sparc",
 .sparc => "elf32_sparc",
 .sparc64 => "elf64_sparc",
 .loongarch32 => "elf32loongarch",
 .loongarch64 => "elf64loongarch",
Expand DownExpand Up@@ -467,13 +466,11 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle,
 .riscv32,
 .sparc,
 .sparcel,
 .thumb,
 .thumbeb,
 .x86,
 .xcore,
 .nvptx,
 .spir,
 .kalimba,
 .lanai,
 .wasm32,
Expand All@@ -487,7 +484,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .aarch64_be => copy.cpu.arch = .armeb,
 .nvptx64 => copy.cpu.arch = .nvptx,
 .wasm64 => copy.cpu.arch = .wasm32,
 .spir64 => copy.cpu.arch = .spir,
 .spirv64 => copy.cpu.arch = .spirv32,
 .loongarch64 => copy.cpu.arch = .loongarch32,
 .mips64 => copy.cpu.arch = .mips,
Expand All@@ -513,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .lanai,
 .m68k,
 .msp430,
 .sparcel,
 .spu_2,
 .xcore,
 .xtensa,
Expand All@@ -526,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .bpfel,
 .nvptx64,
 .wasm64,
 .spir64,
 .spirv64,
 .loongarch64,
 .mips64,
Expand All@@ -550,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle => copy.cpu.arch = .powerpc64le,
 .riscv32 => copy.cpu.arch = .riscv64,
 .sparc => copy.cpu.arch = .sparc64,
 .spir => copy.cpu.arch = .spir64,
 .spirv32 => copy.cpu.arch = .spirv64,
 .thumb => copy.cpu.arch = .aarch64,
 .thumbeb => copy.cpu.arch = .aarch64_be,
Expand DownExpand Up@@ -597,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .riscv64 => "riscv64",
 .sparc => "sparc",
 .sparc64 => "sparc64",
 .sparcel => "sparcel",
 .s390x => "s390x",
 .thumb => "thumb",
 .thumbeb => "thumbeb",
Expand All@@ -607,8 +599,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .xtensa => "xtensa",
 .nvptx => "nvptx",
 .nvptx64 => "nvptx64",
 .spir => "spir",
 .spir64 => "spir64",
 .spirv32 => "spirv32",
 .spirv64 => "spirv64",
 .kalimba => "kalimba",
Expand All@@ -624,8 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {

 const llvm_os = switch (target.os.tag) {
 .freestanding => "unknown",
 .ananas => "ananas",
 .cloudabi => "cloudabi",
 .dragonfly => "dragonfly",
 .freebsd => "freebsd",
 .fuchsia => "fuchsia",
Expand Down

1 change: 0 additions & 1 deletion
lib/compiler/aro/aro/toolchains/Linux.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
 .powerpc,
 .powerpcle,
 .sparc,
 .sparcel,
 => return "lib32",
 else => {},
 }
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/atomics.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
 // On SPARC systems that lacks CAS and/or swap instructions, the only
 // available atomic operation is a test-and-set (`ldstub`), so we force
 // every atomic memory access to go through the lock.
 .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
 .sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,

 // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
 // and set this parameter accordingly.
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/clear_cache.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
 else => false,
 };
 const sparc = switch (arch) {
 .sparc, .sparc64, .sparcel => true,
 .sparc, .sparc64 => true,
 else => false,
 };
 const apple = switch (os) {
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Strip utm_, fbclid, gclid, etc. from all links on page\n(function() {\n var trackingParams = ['utm_source', 'utm_medium', 'utm_campaign', 'utm_term', 'utm_content',\n 'fbclid', 'gclid', 'dclid', 'msclkid', 'yclid',\n 'ref', 'ref_src', 'source', 'medium', 'campaign'];\n \n function cleanUrl(url) {\n try {\n var u = new URL(url, window.location.origin);\n var changed = false;\n trackingParams.forEach(function(p) {\n if (u.searchParams.has(p)) {\n u.searchParams.delete(p);\n changed = true;\n }\n });\n return changed ? u.toString() : url;\n } catch (e) {\n return url;\n }\n }\n \n function cleanLinks() {\n document.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n \n cleanLinks();\n \n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1) {\n if (node.tagName === 'A') cleanLinks();\n node.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Remove Tracking Parameters from Links");
}
} catch(__e) { console.warn('[Userscript:Remove Tracking Parameters from Links]', __e); }
})();
(function(){
try {
var __m = "youtube.com";
var __re = new RegExp('^' + "youtube\\.com" + '

Skip to content
std.Target: Remove more dead OS/architecture tags#20870

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Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

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privacy statement. We’ll occasionally send you account related emails.

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to your account

 Merged

andrewrk
merged 6 commits into

from

Aug 1, 2024
 Merged

std.Target: Remove more dead OS/architecture tags
#20870
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1e9278d

std.Target: Remove `spir`/`spir64` architecture tags.


alexrp Jul 29, 2024
c8ca05e

std.Target: Remove `sparcel` architecture tag.


alexrp Jul 30, 2024
ef06e4b

std.Target: Remove `ananas` OS tag.


alexrp Jul 30, 2024
b49b750

std.Target: Remove `cloudabi` OS tag.


alexrp Jul 30, 2024
c377316

std.Target: Add `tce`/`tcele` to the comment listing omitted architec…


alexrp Jul 30, 2024
62a0185

glibc: Add a temporary hack in abilists loading due to sparcel removal.


alexrp Jul 30, 2024

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4 changes: 2 additions & 2 deletions
lib/compiler/aro/aro/Compilation.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
 \\#define __sparc_v9__ 1
 \\
 ),
 .sparc, .sparcel => try w.writeAll(
 .sparc => try w.writeAll(
 \\#define __sparc__ 1
 \\#define __sparc 1
 \\
Expand DownExpand Up@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi

 if (system_defines_mode == .include_system_defines) {
 try buf.appendSlice(
 \\#define __VERSION__ "Aro
 \\#define __VERSION__ "Aro
 ++ @import("../backend.zig").version_str ++ "\"\n" ++
 \\#define __Aro__
 \\
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler/aro/aro/Driver/GCCDetector.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
 biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
 biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
 },
 .sparc, .sparcel => {
 .sparc => {
 lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
 triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
 biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);
Expand Down

18 changes: 3 additions & 15 deletions
lib/compiler/aro/aro/target.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -53,13 +53,12 @@ pub fn intPtrType(target: std.Target) Type {
 .xcore,
 .hexagon,
 .m68k,
 .spir,
 .spirv32,
 .arc,
 .avr,
 => return .{ .specifier = .int },

 .sparc, .sparcel => switch (target.os.tag) {
 .sparc => switch (target.os.tag) {
 .netbsd, .openbsd => {},
 else => return .{ .specifier = .int },
 },
Expand DownExpand Up@@ -133,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
 return switch (target.cpu.arch) {
 .arm, .armeb => 4,
 .aarch64, .aarch64_be => 4,
 .sparc, .sparcel, .sparc64 => 4,
 .sparc, .sparc64 => 4,
 .riscv64 => 2,
 else => 1,
 };
Expand DownExpand Up@@ -427,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
 .powerpc64le => "elf64lppc",
 .riscv32 => "elf32lriscv",
 .riscv64 => "elf64lriscv",
 .sparc, .sparcel => "elf32_sparc",
 .sparc => "elf32_sparc",
 .sparc64 => "elf64_sparc",
 .loongarch32 => "elf32loongarch",
 .loongarch64 => "elf64loongarch",
Expand DownExpand Up@@ -467,13 +466,11 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle,
 .riscv32,
 .sparc,
 .sparcel,
 .thumb,
 .thumbeb,
 .x86,
 .xcore,
 .nvptx,
 .spir,
 .kalimba,
 .lanai,
 .wasm32,
Expand All@@ -487,7 +484,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .aarch64_be => copy.cpu.arch = .armeb,
 .nvptx64 => copy.cpu.arch = .nvptx,
 .wasm64 => copy.cpu.arch = .wasm32,
 .spir64 => copy.cpu.arch = .spir,
 .spirv64 => copy.cpu.arch = .spirv32,
 .loongarch64 => copy.cpu.arch = .loongarch32,
 .mips64 => copy.cpu.arch = .mips,
Expand All@@ -513,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .lanai,
 .m68k,
 .msp430,
 .sparcel,
 .spu_2,
 .xcore,
 .xtensa,
Expand All@@ -526,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .bpfel,
 .nvptx64,
 .wasm64,
 .spir64,
 .spirv64,
 .loongarch64,
 .mips64,
Expand All@@ -550,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle => copy.cpu.arch = .powerpc64le,
 .riscv32 => copy.cpu.arch = .riscv64,
 .sparc => copy.cpu.arch = .sparc64,
 .spir => copy.cpu.arch = .spir64,
 .spirv32 => copy.cpu.arch = .spirv64,
 .thumb => copy.cpu.arch = .aarch64,
 .thumbeb => copy.cpu.arch = .aarch64_be,
Expand DownExpand Up@@ -597,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .riscv64 => "riscv64",
 .sparc => "sparc",
 .sparc64 => "sparc64",
 .sparcel => "sparcel",
 .s390x => "s390x",
 .thumb => "thumb",
 .thumbeb => "thumbeb",
Expand All@@ -607,8 +599,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .xtensa => "xtensa",
 .nvptx => "nvptx",
 .nvptx64 => "nvptx64",
 .spir => "spir",
 .spir64 => "spir64",
 .spirv32 => "spirv32",
 .spirv64 => "spirv64",
 .kalimba => "kalimba",
Expand All@@ -624,8 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {

 const llvm_os = switch (target.os.tag) {
 .freestanding => "unknown",
 .ananas => "ananas",
 .cloudabi => "cloudabi",
 .dragonfly => "dragonfly",
 .freebsd => "freebsd",
 .fuchsia => "fuchsia",
Expand Down

1 change: 0 additions & 1 deletion
lib/compiler/aro/aro/toolchains/Linux.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
 .powerpc,
 .powerpcle,
 .sparc,
 .sparcel,
 => return "lib32",
 else => {},
 }
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/atomics.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
 // On SPARC systems that lacks CAS and/or swap instructions, the only
 // available atomic operation is a test-and-set (`ldstub`), so we force
 // every atomic memory access to go through the lock.
 .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
 .sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,

 // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
 // and set this parameter accordingly.
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/clear_cache.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
 else => false,
 };
 const sparc = switch (arch) {
 .sparc, .sparc64, .sparcel => true,
 .sparc, .sparc64 => true,
 else => false,
 };
 const apple = switch (os) {
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Auto-enable theater mode on YouTube\n(function() {\n function tryTheater() {\n var btn = document.querySelector('button[aria-label=\"Theater mode\"], ytd-player #player button[title=\"Theater mode\"]');\n if (btn && !btn.classList.contains('activated')) {\n btn.click();\n }\n }\n \n // Try immediately\n tryTheater();\n \n // Try after navigation (SPA)\n var lastUrl = location.href;\n setInterval(function() {\n if (location.href !== lastUrl) {\n lastUrl = location.href;\n setTimeout(tryTheater, 500);\n }\n }, 1000);\n \n // Also try on player load\n var observer = new MutationObserver(tryTheater);\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "YouTube Theater Mode Default");
}
} catch(__e) { console.warn('[Userscript:YouTube Theater Mode Default]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
std.Target: Remove more dead OS/architecture tags#20870

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 Merged

andrewrk
merged 6 commits into

from

Aug 1, 2024
 Merged

std.Target: Remove more dead OS/architecture tags
#20870
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1e9278d

std.Target: Remove `spir`/`spir64` architecture tags.


alexrp Jul 29, 2024
c8ca05e

std.Target: Remove `sparcel` architecture tag.


alexrp Jul 30, 2024
ef06e4b

std.Target: Remove `ananas` OS tag.


alexrp Jul 30, 2024
b49b750

std.Target: Remove `cloudabi` OS tag.


alexrp Jul 30, 2024
c377316

std.Target: Add `tce`/`tcele` to the comment listing omitted architec…


alexrp Jul 30, 2024
62a0185

glibc: Add a temporary hack in abilists loading due to sparcel removal.


alexrp Jul 30, 2024

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4 changes: 2 additions & 2 deletions
lib/compiler/aro/aro/Compilation.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
 \\#define __sparc_v9__ 1
 \\
 ),
 .sparc, .sparcel => try w.writeAll(
 .sparc => try w.writeAll(
 \\#define __sparc__ 1
 \\#define __sparc 1
 \\
Expand DownExpand Up@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi

 if (system_defines_mode == .include_system_defines) {
 try buf.appendSlice(
 \\#define __VERSION__ "Aro
 \\#define __VERSION__ "Aro
 ++ @import("../backend.zig").version_str ++ "\"\n" ++
 \\#define __Aro__
 \\
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler/aro/aro/Driver/GCCDetector.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
 biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
 biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
 },
 .sparc, .sparcel => {
 .sparc => {
 lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
 triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
 biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);
Expand Down

18 changes: 3 additions & 15 deletions
lib/compiler/aro/aro/target.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -53,13 +53,12 @@ pub fn intPtrType(target: std.Target) Type {
 .xcore,
 .hexagon,
 .m68k,
 .spir,
 .spirv32,
 .arc,
 .avr,
 => return .{ .specifier = .int },

 .sparc, .sparcel => switch (target.os.tag) {
 .sparc => switch (target.os.tag) {
 .netbsd, .openbsd => {},
 else => return .{ .specifier = .int },
 },
Expand DownExpand Up@@ -133,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
 return switch (target.cpu.arch) {
 .arm, .armeb => 4,
 .aarch64, .aarch64_be => 4,
 .sparc, .sparcel, .sparc64 => 4,
 .sparc, .sparc64 => 4,
 .riscv64 => 2,
 else => 1,
 };
Expand DownExpand Up@@ -427,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
 .powerpc64le => "elf64lppc",
 .riscv32 => "elf32lriscv",
 .riscv64 => "elf64lriscv",
 .sparc, .sparcel => "elf32_sparc",
 .sparc => "elf32_sparc",
 .sparc64 => "elf64_sparc",
 .loongarch32 => "elf32loongarch",
 .loongarch64 => "elf64loongarch",
Expand DownExpand Up@@ -467,13 +466,11 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle,
 .riscv32,
 .sparc,
 .sparcel,
 .thumb,
 .thumbeb,
 .x86,
 .xcore,
 .nvptx,
 .spir,
 .kalimba,
 .lanai,
 .wasm32,
Expand All@@ -487,7 +484,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .aarch64_be => copy.cpu.arch = .armeb,
 .nvptx64 => copy.cpu.arch = .nvptx,
 .wasm64 => copy.cpu.arch = .wasm32,
 .spir64 => copy.cpu.arch = .spir,
 .spirv64 => copy.cpu.arch = .spirv32,
 .loongarch64 => copy.cpu.arch = .loongarch32,
 .mips64 => copy.cpu.arch = .mips,
Expand All@@ -513,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .lanai,
 .m68k,
 .msp430,
 .sparcel,
 .spu_2,
 .xcore,
 .xtensa,
Expand All@@ -526,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .bpfel,
 .nvptx64,
 .wasm64,
 .spir64,
 .spirv64,
 .loongarch64,
 .mips64,
Expand All@@ -550,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle => copy.cpu.arch = .powerpc64le,
 .riscv32 => copy.cpu.arch = .riscv64,
 .sparc => copy.cpu.arch = .sparc64,
 .spir => copy.cpu.arch = .spir64,
 .spirv32 => copy.cpu.arch = .spirv64,
 .thumb => copy.cpu.arch = .aarch64,
 .thumbeb => copy.cpu.arch = .aarch64_be,
Expand DownExpand Up@@ -597,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .riscv64 => "riscv64",
 .sparc => "sparc",
 .sparc64 => "sparc64",
 .sparcel => "sparcel",
 .s390x => "s390x",
 .thumb => "thumb",
 .thumbeb => "thumbeb",
Expand All@@ -607,8 +599,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .xtensa => "xtensa",
 .nvptx => "nvptx",
 .nvptx64 => "nvptx64",
 .spir => "spir",
 .spir64 => "spir64",
 .spirv32 => "spirv32",
 .spirv64 => "spirv64",
 .kalimba => "kalimba",
Expand All@@ -624,8 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {

 const llvm_os = switch (target.os.tag) {
 .freestanding => "unknown",
 .ananas => "ananas",
 .cloudabi => "cloudabi",
 .dragonfly => "dragonfly",
 .freebsd => "freebsd",
 .fuchsia => "fuchsia",
Expand Down

1 change: 0 additions & 1 deletion
lib/compiler/aro/aro/toolchains/Linux.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
 .powerpc,
 .powerpcle,
 .sparc,
 .sparcel,
 => return "lib32",
 else => {},
 }
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/atomics.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
 // On SPARC systems that lacks CAS and/or swap instructions, the only
 // available atomic operation is a test-and-set (`ldstub`), so we force
 // every atomic memory access to go through the lock.
 .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
 .sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,

 // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
 // and set this parameter accordingly.
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/clear_cache.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
 else => false,
 };
 const sparc = switch (arch) {
 .sparc, .sparc64, .sparcel => true,
 .sparc, .sparc64 => true,
 else => false,
 };
 const apple = switch (os) {
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Remove or un-stick sticky/fixed headers that block content\n(function() {\n function unstick() {\n document.querySelectorAll('header, nav, [role=\"banner\"], .header, .navbar, .sticky, .fixed-top, [style*=\"position: fixed\"], [style*=\"position:sticky\"]').forEach(function(el) {\n if (el.style.position === 'fixed' || el.style.position === 'sticky' || \n getComputedStyle(el).position === 'fixed' || getComputedStyle(el).position === 'sticky') {\n el.style.position = 'static';\n el.style.top = 'auto';\n el.style.zIndex = 'auto';\n }\n });\n }\n \n unstick();\n \n var observer = new MutationObserver(unstick);\n observer.observe(document.body, { childList: true, subtree: true, attributes: true, attributeFilter: ['style', 'class'] });\n})();", "Kill Sticky Headers");
}
} catch(__e) { console.warn('[Userscript:Kill Sticky Headers]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
std.Target: Remove more dead OS/architecture tags#20870

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 Merged

andrewrk
merged 6 commits into

from

Aug 1, 2024
 Merged

std.Target: Remove more dead OS/architecture tags
#20870
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1e9278d

std.Target: Remove `spir`/`spir64` architecture tags.


alexrp Jul 29, 2024
c8ca05e

std.Target: Remove `sparcel` architecture tag.


alexrp Jul 30, 2024
ef06e4b

std.Target: Remove `ananas` OS tag.


alexrp Jul 30, 2024
b49b750

std.Target: Remove `cloudabi` OS tag.


alexrp Jul 30, 2024
c377316

std.Target: Add `tce`/`tcele` to the comment listing omitted architec…


alexrp Jul 30, 2024
62a0185

glibc: Add a temporary hack in abilists loading due to sparcel removal.


alexrp Jul 30, 2024

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4 changes: 2 additions & 2 deletions
lib/compiler/aro/aro/Compilation.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
 \\#define __sparc_v9__ 1
 \\
 ),
 .sparc, .sparcel => try w.writeAll(
 .sparc => try w.writeAll(
 \\#define __sparc__ 1
 \\#define __sparc 1
 \\
Expand DownExpand Up@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi

 if (system_defines_mode == .include_system_defines) {
 try buf.appendSlice(
 \\#define __VERSION__ "Aro
 \\#define __VERSION__ "Aro
 ++ @import("../backend.zig").version_str ++ "\"\n" ++
 \\#define __Aro__
 \\
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler/aro/aro/Driver/GCCDetector.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
 biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
 biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
 },
 .sparc, .sparcel => {
 .sparc => {
 lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
 triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
 biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);
Expand Down

18 changes: 3 additions & 15 deletions
lib/compiler/aro/aro/target.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -53,13 +53,12 @@ pub fn intPtrType(target: std.Target) Type {
 .xcore,
 .hexagon,
 .m68k,
 .spir,
 .spirv32,
 .arc,
 .avr,
 => return .{ .specifier = .int },

 .sparc, .sparcel => switch (target.os.tag) {
 .sparc => switch (target.os.tag) {
 .netbsd, .openbsd => {},
 else => return .{ .specifier = .int },
 },
Expand DownExpand Up@@ -133,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
 return switch (target.cpu.arch) {
 .arm, .armeb => 4,
 .aarch64, .aarch64_be => 4,
 .sparc, .sparcel, .sparc64 => 4,
 .sparc, .sparc64 => 4,
 .riscv64 => 2,
 else => 1,
 };
Expand DownExpand Up@@ -427,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
 .powerpc64le => "elf64lppc",
 .riscv32 => "elf32lriscv",
 .riscv64 => "elf64lriscv",
 .sparc, .sparcel => "elf32_sparc",
 .sparc => "elf32_sparc",
 .sparc64 => "elf64_sparc",
 .loongarch32 => "elf32loongarch",
 .loongarch64 => "elf64loongarch",
Expand DownExpand Up@@ -467,13 +466,11 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle,
 .riscv32,
 .sparc,
 .sparcel,
 .thumb,
 .thumbeb,
 .x86,
 .xcore,
 .nvptx,
 .spir,
 .kalimba,
 .lanai,
 .wasm32,
Expand All@@ -487,7 +484,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .aarch64_be => copy.cpu.arch = .armeb,
 .nvptx64 => copy.cpu.arch = .nvptx,
 .wasm64 => copy.cpu.arch = .wasm32,
 .spir64 => copy.cpu.arch = .spir,
 .spirv64 => copy.cpu.arch = .spirv32,
 .loongarch64 => copy.cpu.arch = .loongarch32,
 .mips64 => copy.cpu.arch = .mips,
Expand All@@ -513,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .lanai,
 .m68k,
 .msp430,
 .sparcel,
 .spu_2,
 .xcore,
 .xtensa,
Expand All@@ -526,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .bpfel,
 .nvptx64,
 .wasm64,
 .spir64,
 .spirv64,
 .loongarch64,
 .mips64,
Expand All@@ -550,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle => copy.cpu.arch = .powerpc64le,
 .riscv32 => copy.cpu.arch = .riscv64,
 .sparc => copy.cpu.arch = .sparc64,
 .spir => copy.cpu.arch = .spir64,
 .spirv32 => copy.cpu.arch = .spirv64,
 .thumb => copy.cpu.arch = .aarch64,
 .thumbeb => copy.cpu.arch = .aarch64_be,
Expand DownExpand Up@@ -597,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .riscv64 => "riscv64",
 .sparc => "sparc",
 .sparc64 => "sparc64",
 .sparcel => "sparcel",
 .s390x => "s390x",
 .thumb => "thumb",
 .thumbeb => "thumbeb",
Expand All@@ -607,8 +599,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .xtensa => "xtensa",
 .nvptx => "nvptx",
 .nvptx64 => "nvptx64",
 .spir => "spir",
 .spir64 => "spir64",
 .spirv32 => "spirv32",
 .spirv64 => "spirv64",
 .kalimba => "kalimba",
Expand All@@ -624,8 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {

 const llvm_os = switch (target.os.tag) {
 .freestanding => "unknown",
 .ananas => "ananas",
 .cloudabi => "cloudabi",
 .dragonfly => "dragonfly",
 .freebsd => "freebsd",
 .fuchsia => "fuchsia",
Expand Down

1 change: 0 additions & 1 deletion
lib/compiler/aro/aro/toolchains/Linux.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
 .powerpc,
 .powerpcle,
 .sparc,
 .sparcel,
 => return "lib32",
 else => {},
 }
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/atomics.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
 // On SPARC systems that lacks CAS and/or swap instructions, the only
 // available atomic operation is a test-and-set (`ldstub`), so we force
 // every atomic memory access to go through the lock.
 .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
 .sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,

 // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
 // and set this parameter accordingly.
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/clear_cache.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
 else => false,
 };
 const sparc = switch (arch) {
 .sparc, .sparc64, .sparcel => true,
 .sparc, .sparc64 => true,
 else => false,
 };
 const apple = switch (os) {
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Universal Dark Mode - works on any site\n(function() {\n var enabled = true;\n \n function applyDarkMode() {\n if (!enabled) return;\n \n // Create style element if it doesn't exist\n var style = document.getElementById('universal-dark-mode-style');\n if (!style) {\n style = document.createElement('style');\n style.id = 'universal-dark-mode-style';\n document.head.appendChild(style);\n }\n \n // Dark mode CSS - inverts colors but preserves images/video\n style.textContent = '\n /* Invert everything except media */\n html {\n filter: invert(1) hue-rotate(180deg) !important;\n background: #1a1a2e !important;\n }\n \n /* Restore images, videos, iframes, canvas */\n img, video, iframe, canvas, svg, picture, [style*=\"background-image\"] {\n filter: invert(1) hue-rotate(180deg) !important;\n }\n \n /* Preserve specific elements that should not be inverted */\n .no-dark-mode, .no-dark-mode *,\n [data-theme=\"light\"], [data-theme=\"light\"],\n .ace_editor, .ace_editor *,\n .CodeMirror, .CodeMirror *,\n .monaco-editor, .monaco-editor *,\n .markdown-body pre, .markdown-body pre *,\n .highlight, .highlight *,\n pre code, pre code * {\n filter: none !important;\n }\n \n /* Fix common UI elements */\n .modal, .popup, .dropdown-menu, .tooltip, .popover {\n filter: invert(1) hue-rotate(180deg) !important;\n background: #2d2d44 !important;\n border-color: #444 !important;\n }\n \n /* Scrollbars */\n ::-webkit-scrollbar { background: #1a1a2e !important; }\n ::-webkit-scrollbar-thumb { background: #444 !important; }\n ::-webkit-scrollbar-thumb:hover { background: #555 !important; }\n \n /* Selection */\n ::selection { background: #4ecdc4 !important; color: #1a1a2e !important; }\n ::-moz-selection { background: #4ecdc4 !important; color: #1a1a2e !important; }\n ';\n }\n \n function removeDarkMode() {\n var style = document.getElementById('universal-dark-mode-style');\n if (style) style.remove();\n }\n \n // Toggle with Alt+Shift+D\n document.addEventListener('keydown', function(e) {\n if (e.altKey && e.shiftKey && e.key === 'D') {\n e.preventDefault();\n enabled = !enabled;\n if (enabled) {\n applyDarkMode();\n console.log('[Universal Dark Mode] Enabled');\n } else {\n removeDarkMode();\n console.log('[Universal Dark Mode] Disabled');\n }\n }\n });\n \n // Apply on load\n applyDarkMode();\n \n // Re-apply on dynamic content\n var observer = new MutationObserver(function(mutations) {\n if (enabled && !document.getElementById('universal-dark-mode-style')) {\n applyDarkMode();\n }\n });\n observer.observe(document.head, { childList: true });\n \n console.log('[Universal Dark Mode] Loaded - Press Alt+Shift+D to toggle');\n})();", "Universal Dark Mode");
}
} catch(__e) { console.warn('[Userscript:Universal Dark Mode]', __e); }
})();
})();

Skip to content
std.Target: Remove more dead OS/architecture tags#20870

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Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

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privacy statement. We’ll occasionally send you account related emails.

Already on GitHub?
Sign in
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 Merged

andrewrk
merged 6 commits into

from

Aug 1, 2024
 Merged

std.Target: Remove more dead OS/architecture tags
#20870
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1e9278d

std.Target: Remove `spir`/`spir64` architecture tags.


alexrp Jul 29, 2024
c8ca05e

std.Target: Remove `sparcel` architecture tag.


alexrp Jul 30, 2024
ef06e4b

std.Target: Remove `ananas` OS tag.


alexrp Jul 30, 2024
b49b750

std.Target: Remove `cloudabi` OS tag.


alexrp Jul 30, 2024
c377316

std.Target: Add `tce`/`tcele` to the comment listing omitted architec…


alexrp Jul 30, 2024
62a0185

glibc: Add a temporary hack in abilists loading due to sparcel removal.


alexrp Jul 30, 2024

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4 changes: 2 additions & 2 deletions
lib/compiler/aro/aro/Compilation.zig

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
 \\#define __sparc_v9__ 1
 \\
 ),
 .sparc, .sparcel => try w.writeAll(
 .sparc => try w.writeAll(
 \\#define __sparc__ 1
 \\#define __sparc 1
 \\
Expand DownExpand Up@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi

 if (system_defines_mode == .include_system_defines) {
 try buf.appendSlice(
 \\#define __VERSION__ "Aro
 \\#define __VERSION__ "Aro
 ++ @import("../backend.zig").version_str ++ "\"\n" ++
 \\#define __Aro__
 \\
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler/aro/aro/Driver/GCCDetector.zig

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Original file line numberDiff line numberDiff line change
Expand Up@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
 biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
 biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
 },
 .sparc, .sparcel => {
 .sparc => {
 lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
 triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
 biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);
Expand Down

18 changes: 3 additions & 15 deletions
lib/compiler/aro/aro/target.zig

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Original file line numberDiff line numberDiff line change
Expand Up@@ -53,13 +53,12 @@ pub fn intPtrType(target: std.Target) Type {
 .xcore,
 .hexagon,
 .m68k,
 .spir,
 .spirv32,
 .arc,
 .avr,
 => return .{ .specifier = .int },

 .sparc, .sparcel => switch (target.os.tag) {
 .sparc => switch (target.os.tag) {
 .netbsd, .openbsd => {},
 else => return .{ .specifier = .int },
 },
Expand DownExpand Up@@ -133,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
 return switch (target.cpu.arch) {
 .arm, .armeb => 4,
 .aarch64, .aarch64_be => 4,
 .sparc, .sparcel, .sparc64 => 4,
 .sparc, .sparc64 => 4,
 .riscv64 => 2,
 else => 1,
 };
Expand DownExpand Up@@ -427,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
 .powerpc64le => "elf64lppc",
 .riscv32 => "elf32lriscv",
 .riscv64 => "elf64lriscv",
 .sparc, .sparcel => "elf32_sparc",
 .sparc => "elf32_sparc",
 .sparc64 => "elf64_sparc",
 .loongarch32 => "elf32loongarch",
 .loongarch64 => "elf64loongarch",
Expand DownExpand Up@@ -467,13 +466,11 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle,
 .riscv32,
 .sparc,
 .sparcel,
 .thumb,
 .thumbeb,
 .x86,
 .xcore,
 .nvptx,
 .spir,
 .kalimba,
 .lanai,
 .wasm32,
Expand All@@ -487,7 +484,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 .aarch64_be => copy.cpu.arch = .armeb,
 .nvptx64 => copy.cpu.arch = .nvptx,
 .wasm64 => copy.cpu.arch = .wasm32,
 .spir64 => copy.cpu.arch = .spir,
 .spirv64 => copy.cpu.arch = .spirv32,
 .loongarch64 => copy.cpu.arch = .loongarch32,
 .mips64 => copy.cpu.arch = .mips,
Expand All@@ -513,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .lanai,
 .m68k,
 .msp430,
 .sparcel,
 .spu_2,
 .xcore,
 .xtensa,
Expand All@@ -526,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .bpfel,
 .nvptx64,
 .wasm64,
 .spir64,
 .spirv64,
 .loongarch64,
 .mips64,
Expand All@@ -550,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
 .powerpcle => copy.cpu.arch = .powerpc64le,
 .riscv32 => copy.cpu.arch = .riscv64,
 .sparc => copy.cpu.arch = .sparc64,
 .spir => copy.cpu.arch = .spir64,
 .spirv32 => copy.cpu.arch = .spirv64,
 .thumb => copy.cpu.arch = .aarch64,
 .thumbeb => copy.cpu.arch = .aarch64_be,
Expand DownExpand Up@@ -597,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .riscv64 => "riscv64",
 .sparc => "sparc",
 .sparc64 => "sparc64",
 .sparcel => "sparcel",
 .s390x => "s390x",
 .thumb => "thumb",
 .thumbeb => "thumbeb",
Expand All@@ -607,8 +599,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 .xtensa => "xtensa",
 .nvptx => "nvptx",
 .nvptx64 => "nvptx64",
 .spir => "spir",
 .spir64 => "spir64",
 .spirv32 => "spirv32",
 .spirv64 => "spirv64",
 .kalimba => "kalimba",
Expand All@@ -624,8 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {

 const llvm_os = switch (target.os.tag) {
 .freestanding => "unknown",
 .ananas => "ananas",
 .cloudabi => "cloudabi",
 .dragonfly => "dragonfly",
 .freebsd => "freebsd",
 .fuchsia => "fuchsia",
Expand Down

1 change: 0 additions & 1 deletion
lib/compiler/aro/aro/toolchains/Linux.zig

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Original file line numberDiff line numberDiff line change
Expand Up@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
 .powerpc,
 .powerpcle,
 .sparc,
 .sparcel,
 => return "lib32",
 else => {},
 }
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/atomics.zig

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Original file line numberDiff line numberDiff line change
Expand Up@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
 // On SPARC systems that lacks CAS and/or swap instructions, the only
 // available atomic operation is a test-and-set (`ldstub`), so we force
 // every atomic memory access to go through the lock.
 .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
 .sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,

 // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
 // and set this parameter accordingly.
Expand Down

2 changes: 1 addition & 1 deletion
lib/compiler_rt/clear_cache.zig

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Original file line numberDiff line numberDiff line change
Expand Up@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
 else => false,
 };
 const sparc = switch (arch) {
 .sparc, .sparc64, .sparcel => true,
 .sparc, .sparc64 => true,
 else => false,
 };
 const apple = switch (os) {
Expand Down
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