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AuringzaibSabir/README.md

Hello World! 👋 I'm Auringzaib Sabir - Design Verification Engineer & Research Associate

I am (!Gold_Medalist || !Failure)

Over the last few years, I have been serving in the semiconductor industry as a hardware verification engineer. I have developed expertise in verification methodologies like UVM, System Verilog, Functional verification, Functional coverages, Python, PCIe, and CXL. I have gained considerable knowledge in the field of semiconductors.

Top LangsAuringzaib's GitHub stats

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Languages and Tools:

System VerilogUVMRISC-VPythonsynosyscadence

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  1. azadi-verifyazadi-verifyPublic

    Forked from merledu/azadi-verify

    This repository contains tests (in C and assembly both), benchmarks and the test-benches for the verification of Azadi SoC.

    Assembly

  2. common_peripheral_vipscommon_peripheral_vipsPublic

    Forked from merledu/common_peripheral_vips

    SystemVerilog

  3. azadi-newazadi-newPublic

    Forked from merledu/azadi-soc

    Azadi after tapeout

    SystemVerilog

  4. python_projectpython_projectPublic

    Python

  5. uvm_sampleuvm_samplePublic

    This repository contains a sample code of the UVM environment. Use this code as a reference for writing a complex UVM framework.

    SystemVerilog 3 2