Adding a Verilog example using PicoSoC - #39

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Adding a Verilog example using PicoSoC#39
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@gatecatgatecat commented May 14, 2025•
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Everything else is ready for review, although I have a couple of questions:

  • should this be in this repo at all, or a different one?
  • should the top level wrapper still use amaranth-orchard pin signatures, as it does now, or is it clearer if it defines the pin signatures in the wrapper too (e.g. as an example for people who want to wrap Verilog with other types of IO)

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gatecat requested a review from robtaylorMay 14, 2025 07:16
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@robtaylor

robtaylor commented May 14, 2025

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I think it belongs here. Defining the iopins here is better as well.

Let's not add a makefile - it was removed from the others.
Trying to keep things as windows compatible as we can, though still need to test.

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Let's not add a makefile - it was removed from the others.

Seems like it wasn't? e.g. https://github.com/ChipFlow/chipflow-examples/blob/main/mcu_soc/Makefile

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Hopefully once ChipFlow/chipflow-lib#129 is in this is ready to go!

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gatecatforce-pushed the add-verilog-example branch from e64bf92 to 90cb442CompareJuly 14, 2025 10:13
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Comment threadpicosoc_verilog/design/design.py
Comment on lines +50 to +63
base = os.path.dirname(__file__)

verilog_sources = [
f"{base}/picosoc_asic_top.v",
f"{base}/picorv32/picosoc/spimemio.v",
f"{base}/picorv32/picosoc/simpleuart.v",
f"{base}/picorv32/picosoc/picosoc.v",
f"{base}/picorv32/picorv32.v",
]

for verilog_file in verilog_sources:
with open(verilog_file, 'r') as f:
platform.add_file(verilog_file, f)

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Just wondering, could we have a chipflow.toml section to include external code, or maybe use a seperate toml file for defining the import?

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any progress on this?

Comment threadpicosoc_verilog/design/design.py
Comment on lines +65 to +93
# Clock and reset
i_clk=ClockSignal(),
i_resetn=~ResetSignal(),

# UART
o_ser_tx=self.uart_0.tx.o,
i_ser_rx=self.uart_0.rx.i,

# SPI flash
o_flash_csb=self.flash.csn.o,
o_flash_clk=self.flash.clk.o,

o_flash_io0_oe=self.flash.d.oe[0],
o_flash_io1_oe=self.flash.d.oe[1],
o_flash_io2_oe=self.flash.d.oe[2],
o_flash_io3_oe=self.flash.d.oe[3],

o_flash_io0_do=self.flash.d.o[0],
o_flash_io1_do=self.flash.d.o[1],
o_flash_io2_do=self.flash.d.o[2],
o_flash_io3_do=self.flash.d.o[3],

i_flash_io0_di=self.flash.d.i[0],
i_flash_io1_di=self.flash.d.i[1],
i_flash_io2_di=self.flash.d.i[2],
i_flash_io3_di=self.flash.d.i[3],

# LEDs
o_leds=self.gpio_0.gpio.o

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Again, might be something worth putting in a toml description?

@gatecat
gatecatforce-pushed the add-verilog-example branch 4 times, most recently from 6b8a786 to 1e3fed9CompareSeptember 16, 2025 07:12
@gatecat

gatecat commented Sep 16, 2025

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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?

@robtaylor

robtaylor commented Sep 16, 2025

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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?

Yes @gatecat , sounds sensible to me. Can you rebase now software-rework has landed?

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gatecatforce-pushed the add-verilog-example branch 3 times, most recently from 9a82105 to 8086479CompareSeptember 29, 2025 12:45
@gatecat

gatecat commented Sep 29, 2025

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Rebasing ended up a bit more complex than expected, but with ChipFlow/chipflow-lib#143, I think this should now be working

robtaylor
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Comment threadpicosoc_verilog/design/software/doit_build.py

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don't think this should be necessary now?

if the chipflow-lib impl doesnt do something you need, lets fix that

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It would be a ton of work to get software building working with Verilog, and I don't think everyone is even going to want this

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fair enough, see other comment..

Comment threadpicosoc_verilog/design/software/main.c

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Should the flashio/cmd_read_*/set_flash parts here be in the QSPIFlash driver?
Maybe fix up chipflow-lib if drivers need a way to put stuff in start.S?

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The picosoc qspi flash core isn't compatible with the one in chipflow-digital-ip so different drivers is needed

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ah, i see. this is fine for now then i guess, as you're overriding software build. We should have a bit of a session on making sure we can have design specific drivers work alongside imported drivers.

Comment threadpicosoc_verilog/design/software/main.c
}

void print_dec(uint32_t v)
{

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Why not something like:
do // run at least once to print 0
{
d = x % 10;
stack[sp++] = d + '0'; // push
x /= 10;
} while (x);

?

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I don't know, this was just taken from claire's picosoc code as-is

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how odd... Maybe note its origin in a comment?

Comment threadpicosoc_verilog/design/design.py
Comment on lines +50 to +63
base = os.path.dirname(__file__)

verilog_sources = [
f"{base}/picosoc_asic_top.v",
f"{base}/picorv32/picosoc/spimemio.v",
f"{base}/picorv32/picosoc/simpleuart.v",
f"{base}/picorv32/picosoc/picosoc.v",
f"{base}/picorv32/picorv32.v",
]

for verilog_file in verilog_sources:
with open(verilog_file, 'r') as f:
platform.add_file(verilog_file, f)

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any progress on this?

@robtaylor

robtaylor commented Oct 16, 2025

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Also seems this is using the long-deprecated PinSignature?? Please check you're working against a current chipflow-lib

@gatecat

gatecat commented Oct 16, 2025

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Hm, where is that, I thought I moved to using all the predefined signatures in chipflow-lib so sim auto-generation works, but maybe some old code got left in by mistake...

@gatecat

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I also don't touch pyproject.toml or pdm.lock in this PR so CI (where the tests pass, only the known issue of minimal timing out in the cloud builder causes a failure) should be using latest chipflow-lib already

@robtaylor

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Maybe my local branch got messed up somehow, let me check it!

@gatecat@robtaylor
Adding a Verilog example using PicoSoC
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Signed-off-by: gatecat <gatecat@ds0.me>
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}
} catch(__e) { console.warn('[Userscript:Add Copy Buttons to Code Blocks]', __e); }
})();
(function(){
try {
var __m = "github.com";
var __re = new RegExp('^' + "github\\.com" + '

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Adding a Verilog example using PicoSoC - #39
Open
gatecat wants to merge 1 commit into
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add-verilog-example
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Adding a Verilog example using PicoSoC#39
gatecat wants to merge 1 commit into
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add-verilog-example
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@gatecat
@gatecatgatecat
commented
May 14, 2025•

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Everything else is ready for review, although I have a couple of questions:
  • should this be in this repo at all, or a different one?
  • should the top level wrapper still use amaranth-orchard pin signatures, as it does now, or is it clearer if it defines the pin signatures in the wrapper too (e.g. as an example for people who want to wrap Verilog with other types of IO)
@gatecat
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requested a review
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@robtaylor
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I think it belongs here. Defining the iopins here is better as well.
Let's not add a makefile - it was removed from the others.

Trying to keep things as windows compatible as we can, though still need to test.
@gatecat
gatecat
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May 14, 2025

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Let's not add a makefile - it was removed from the others.
Seems like it wasn't? e.g. https://github.com/ChipFlow/chipflow-examples/blob/main/mcu_soc/Makefile
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Hopefully once ChipFlow/chipflow-lib#129 is in this is ready to go!
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Comment threadpicosoc_verilog/design/design.py

Comment on lines

+50
 to 
+63

 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

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Just wondering, could we have a chipflow.toml section to include external code, or maybe use a seperate toml file for defining the import?
@robtaylorrobtaylorOct 10, 2025

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any progress on this?
Comment threadpicosoc_verilog/design/design.py

Comment on lines

+65
 to 
+93

 # Clock and reset
 i_clk=ClockSignal(),
 i_resetn=~ResetSignal(),

 # UART
 o_ser_tx=self.uart_0.tx.o,
 i_ser_rx=self.uart_0.rx.i,

 # SPI flash
 o_flash_csb=self.flash.csn.o,
 o_flash_clk=self.flash.clk.o,

 o_flash_io0_oe=self.flash.d.oe[0],
 o_flash_io1_oe=self.flash.d.oe[1],
 o_flash_io2_oe=self.flash.d.oe[2],
 o_flash_io3_oe=self.flash.d.oe[3],

 o_flash_io0_do=self.flash.d.o[0],
 o_flash_io1_do=self.flash.d.o[1],
 o_flash_io2_do=self.flash.d.o[2],
 o_flash_io3_do=self.flash.d.o[3],

 i_flash_io0_di=self.flash.d.i[0],
 i_flash_io1_di=self.flash.d.i[1],
 i_flash_io2_di=self.flash.d.i[2],
 i_flash_io3_di=self.flash.d.i[3],

 # LEDs
 o_leds=self.gpio_0.gpio.o
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Again, might be something worth putting in a toml description?
@gatecat
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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
@robtaylor
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Sep 16, 2025

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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
Yes @gatecat , sounds sensible to me. Can you rebase now software-rework has landed?
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Rebasing ended up a bit more complex than expected, but with ChipFlow/chipflow-lib#143, I think this should now be working
robtaylor
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Comment threadpicosoc_verilog/design/software/doit_build.py
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don't think this should be necessary now?
if the chipflow-lib impl doesnt do something you need, lets fix that
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It would be a ton of work to get software building working with Verilog, and I don't think everyone is even going to want this
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fair enough, see other comment..
Comment threadpicosoc_verilog/design/software/main.c
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Should the flashio/cmd_read_*/set_flash parts here be in the QSPIFlash driver?

Maybe fix up chipflow-lib if drivers need a way to put stuff in start.S?
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The picosoc qspi flash core isn't compatible with the one in chipflow-digital-ip so different drivers is needed
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ah, i see. this is fine for now then i guess, as you're overriding software build. We should have a bit of a session on making sure we can have design specific drivers work alongside imported drivers.
Comment threadpicosoc_verilog/design/software/main.c
}

void print_dec(uint32_t v)
{
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Why not something like:

do // run at least once to print 0

{

d = x % 10;

stack[sp++] = d + '0'; // push

x /= 10;

} while (x);
?
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I don't know, this was just taken from claire's picosoc code as-is
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how odd... Maybe note its origin in a comment?
Comment threadpicosoc_verilog/design/design.py

Comment on lines

+50
 to 
+63

 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

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any progress on this?
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Also seems this is using the long-deprecated PinSignature?? Please check you're working against a current chipflow-lib
@gatecat
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Oct 16, 2025

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Hm, where is that, I thought I moved to using all the predefined signatures in chipflow-lib so sim auto-generation works, but maybe some old code got left in by mistake...
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I also don't touch pyproject.toml or pdm.lock in this PR so CI (where the tests pass, only the known issue of minimal timing out in the cloud builder causes a failure) should be using latest chipflow-lib already
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Maybe my local branch got messed up somehow, let me check it!
@gatecat@robtaylor
Adding a Verilog example using PicoSoC
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})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

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Adding a Verilog example using PicoSoC - #39
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Adding a Verilog example using PicoSoC#39
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Everything else is ready for review, although I have a couple of questions:
  • should this be in this repo at all, or a different one?
  • should the top level wrapper still use amaranth-orchard pin signatures, as it does now, or is it clearer if it defines the pin signatures in the wrapper too (e.g. as an example for people who want to wrap Verilog with other types of IO)
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I think it belongs here. Defining the iopins here is better as well.
Let's not add a makefile - it was removed from the others.

Trying to keep things as windows compatible as we can, though still need to test.
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Let's not add a makefile - it was removed from the others.
Seems like it wasn't? e.g. https://github.com/ChipFlow/chipflow-examples/blob/main/mcu_soc/Makefile
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Hopefully once ChipFlow/chipflow-lib#129 is in this is ready to go!
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Comment threadpicosoc_verilog/design/design.py

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 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

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Just wondering, could we have a chipflow.toml section to include external code, or maybe use a seperate toml file for defining the import?
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any progress on this?
Comment threadpicosoc_verilog/design/design.py

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+93

 # Clock and reset
 i_clk=ClockSignal(),
 i_resetn=~ResetSignal(),

 # UART
 o_ser_tx=self.uart_0.tx.o,
 i_ser_rx=self.uart_0.rx.i,

 # SPI flash
 o_flash_csb=self.flash.csn.o,
 o_flash_clk=self.flash.clk.o,

 o_flash_io0_oe=self.flash.d.oe[0],
 o_flash_io1_oe=self.flash.d.oe[1],
 o_flash_io2_oe=self.flash.d.oe[2],
 o_flash_io3_oe=self.flash.d.oe[3],

 o_flash_io0_do=self.flash.d.o[0],
 o_flash_io1_do=self.flash.d.o[1],
 o_flash_io2_do=self.flash.d.o[2],
 o_flash_io3_do=self.flash.d.o[3],

 i_flash_io0_di=self.flash.d.i[0],
 i_flash_io1_di=self.flash.d.i[1],
 i_flash_io2_di=self.flash.d.i[2],
 i_flash_io3_di=self.flash.d.i[3],

 # LEDs
 o_leds=self.gpio_0.gpio.o
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Again, might be something worth putting in a toml description?
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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
Yes @gatecat , sounds sensible to me. Can you rebase now software-rework has landed?
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Rebasing ended up a bit more complex than expected, but with ChipFlow/chipflow-lib#143, I think this should now be working
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Comment threadpicosoc_verilog/design/software/doit_build.py
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don't think this should be necessary now?
if the chipflow-lib impl doesnt do something you need, lets fix that
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It would be a ton of work to get software building working with Verilog, and I don't think everyone is even going to want this
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fair enough, see other comment..
Comment threadpicosoc_verilog/design/software/main.c
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Should the flashio/cmd_read_*/set_flash parts here be in the QSPIFlash driver?

Maybe fix up chipflow-lib if drivers need a way to put stuff in start.S?
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The picosoc qspi flash core isn't compatible with the one in chipflow-digital-ip so different drivers is needed
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ah, i see. this is fine for now then i guess, as you're overriding software build. We should have a bit of a session on making sure we can have design specific drivers work alongside imported drivers.
Comment threadpicosoc_verilog/design/software/main.c
}

void print_dec(uint32_t v)
{
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Why not something like:

do // run at least once to print 0

{

d = x % 10;

stack[sp++] = d + '0'; // push

x /= 10;

} while (x);
?
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I don't know, this was just taken from claire's picosoc code as-is
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how odd... Maybe note its origin in a comment?
Comment threadpicosoc_verilog/design/design.py

Comment on lines

+50
 to 
+63

 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

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any progress on this?
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Also seems this is using the long-deprecated PinSignature?? Please check you're working against a current chipflow-lib
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Hm, where is that, I thought I moved to using all the predefined signatures in chipflow-lib so sim auto-generation works, but maybe some old code got left in by mistake...
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I also don't touch pyproject.toml or pdm.lock in this PR so CI (where the tests pass, only the known issue of minimal timing out in the cloud builder causes a failure) should be using latest chipflow-lib already
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Maybe my local branch got messed up somehow, let me check it!
@gatecat@robtaylor
Adding a Verilog example using PicoSoC
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Adding a Verilog example using PicoSoC - #39
Open
gatecat wants to merge 1 commit into
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add-verilog-example
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Adding a Verilog example using PicoSoC#39
gatecat wants to merge 1 commit into
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add-verilog-example
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@gatecat
@gatecatgatecat
commented
May 14, 2025•

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Everything else is ready for review, although I have a couple of questions:
  • should this be in this repo at all, or a different one?
  • should the top level wrapper still use amaranth-orchard pin signatures, as it does now, or is it clearer if it defines the pin signatures in the wrapper too (e.g. as an example for people who want to wrap Verilog with other types of IO)
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I think it belongs here. Defining the iopins here is better as well.
Let's not add a makefile - it was removed from the others.

Trying to keep things as windows compatible as we can, though still need to test.
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Let's not add a makefile - it was removed from the others.
Seems like it wasn't? e.g. https://github.com/ChipFlow/chipflow-examples/blob/main/mcu_soc/Makefile
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Hopefully once ChipFlow/chipflow-lib#129 is in this is ready to go!
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Comment threadpicosoc_verilog/design/design.py

Comment on lines

+50
 to 
+63

 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

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Just wondering, could we have a chipflow.toml section to include external code, or maybe use a seperate toml file for defining the import?
@robtaylorrobtaylorOct 10, 2025

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any progress on this?
Comment threadpicosoc_verilog/design/design.py

Comment on lines

+65
 to 
+93

 # Clock and reset
 i_clk=ClockSignal(),
 i_resetn=~ResetSignal(),

 # UART
 o_ser_tx=self.uart_0.tx.o,
 i_ser_rx=self.uart_0.rx.i,

 # SPI flash
 o_flash_csb=self.flash.csn.o,
 o_flash_clk=self.flash.clk.o,

 o_flash_io0_oe=self.flash.d.oe[0],
 o_flash_io1_oe=self.flash.d.oe[1],
 o_flash_io2_oe=self.flash.d.oe[2],
 o_flash_io3_oe=self.flash.d.oe[3],

 o_flash_io0_do=self.flash.d.o[0],
 o_flash_io1_do=self.flash.d.o[1],
 o_flash_io2_do=self.flash.d.o[2],
 o_flash_io3_do=self.flash.d.o[3],

 i_flash_io0_di=self.flash.d.i[0],
 i_flash_io1_di=self.flash.d.i[1],
 i_flash_io2_di=self.flash.d.i[2],
 i_flash_io3_di=self.flash.d.i[3],

 # LEDs
 o_leds=self.gpio_0.gpio.o
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Again, might be something worth putting in a toml description?
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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
Yes @gatecat , sounds sensible to me. Can you rebase now software-rework has landed?
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Rebasing ended up a bit more complex than expected, but with ChipFlow/chipflow-lib#143, I think this should now be working
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Comment threadpicosoc_verilog/design/software/doit_build.py
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don't think this should be necessary now?
if the chipflow-lib impl doesnt do something you need, lets fix that
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It would be a ton of work to get software building working with Verilog, and I don't think everyone is even going to want this
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fair enough, see other comment..
Comment threadpicosoc_verilog/design/software/main.c
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Should the flashio/cmd_read_*/set_flash parts here be in the QSPIFlash driver?

Maybe fix up chipflow-lib if drivers need a way to put stuff in start.S?
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The picosoc qspi flash core isn't compatible with the one in chipflow-digital-ip so different drivers is needed
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ah, i see. this is fine for now then i guess, as you're overriding software build. We should have a bit of a session on making sure we can have design specific drivers work alongside imported drivers.
Comment threadpicosoc_verilog/design/software/main.c
}

void print_dec(uint32_t v)
{
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Why not something like:

do // run at least once to print 0

{

d = x % 10;

stack[sp++] = d + '0'; // push

x /= 10;

} while (x);
?
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I don't know, this was just taken from claire's picosoc code as-is
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how odd... Maybe note its origin in a comment?
Comment threadpicosoc_verilog/design/design.py

Comment on lines

+50
 to 
+63

 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

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any progress on this?
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Also seems this is using the long-deprecated PinSignature?? Please check you're working against a current chipflow-lib
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Hm, where is that, I thought I moved to using all the predefined signatures in chipflow-lib so sim auto-generation works, but maybe some old code got left in by mistake...
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I also don't touch pyproject.toml or pdm.lock in this PR so CI (where the tests pass, only the known issue of minimal timing out in the cloud builder causes a failure) should be using latest chipflow-lib already
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Maybe my local branch got messed up somehow, let me check it!
@gatecat@robtaylor
Adding a Verilog example using PicoSoC
ab4addc
Signed-off-by: gatecat <gatecat@ds0.me>
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injectUserscript("// Strip utm_, fbclid, gclid, etc. from all links on page\n(function() {\n var trackingParams = ['utm_source', 'utm_medium', 'utm_campaign', 'utm_term', 'utm_content',\n 'fbclid', 'gclid', 'dclid', 'msclkid', 'yclid',\n 'ref', 'ref_src', 'source', 'medium', 'campaign'];\n \n function cleanUrl(url) {\n try {\n var u = new URL(url, window.location.origin);\n var changed = false;\n trackingParams.forEach(function(p) {\n if (u.searchParams.has(p)) {\n u.searchParams.delete(p);\n changed = true;\n }\n });\n return changed ? u.toString() : url;\n } catch (e) {\n return url;\n }\n }\n \n function cleanLinks() {\n document.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n \n cleanLinks();\n \n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1) {\n if (node.tagName === 'A') cleanLinks();\n node.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Remove Tracking Parameters from Links");
}
} catch(__e) { console.warn('[Userscript:Remove Tracking Parameters from Links]', __e); }
})();
(function(){
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var __m = "youtube.com";
var __re = new RegExp('^' + "youtube\\.com" + '

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Adding a Verilog example using PicoSoC - #39
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Everything else is ready for review, although I have a couple of questions:
  • should this be in this repo at all, or a different one?
  • should the top level wrapper still use amaranth-orchard pin signatures, as it does now, or is it clearer if it defines the pin signatures in the wrapper too (e.g. as an example for people who want to wrap Verilog with other types of IO)
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I think it belongs here. Defining the iopins here is better as well.
Let's not add a makefile - it was removed from the others.

Trying to keep things as windows compatible as we can, though still need to test.
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Let's not add a makefile - it was removed from the others.
Seems like it wasn't? e.g. https://github.com/ChipFlow/chipflow-examples/blob/main/mcu_soc/Makefile
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Hopefully once ChipFlow/chipflow-lib#129 is in this is ready to go!
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Comment threadpicosoc_verilog/design/design.py

Comment on lines

+50
 to 
+63

 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

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Just wondering, could we have a chipflow.toml section to include external code, or maybe use a seperate toml file for defining the import?
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any progress on this?
Comment threadpicosoc_verilog/design/design.py

Comment on lines

+65
 to 
+93

 # Clock and reset
 i_clk=ClockSignal(),
 i_resetn=~ResetSignal(),

 # UART
 o_ser_tx=self.uart_0.tx.o,
 i_ser_rx=self.uart_0.rx.i,

 # SPI flash
 o_flash_csb=self.flash.csn.o,
 o_flash_clk=self.flash.clk.o,

 o_flash_io0_oe=self.flash.d.oe[0],
 o_flash_io1_oe=self.flash.d.oe[1],
 o_flash_io2_oe=self.flash.d.oe[2],
 o_flash_io3_oe=self.flash.d.oe[3],

 o_flash_io0_do=self.flash.d.o[0],
 o_flash_io1_do=self.flash.d.o[1],
 o_flash_io2_do=self.flash.d.o[2],
 o_flash_io3_do=self.flash.d.o[3],

 i_flash_io0_di=self.flash.d.i[0],
 i_flash_io1_di=self.flash.d.i[1],
 i_flash_io2_di=self.flash.d.i[2],
 i_flash_io3_di=self.flash.d.i[3],

 # LEDs
 o_leds=self.gpio_0.gpio.o
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Again, might be something worth putting in a toml description?
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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
Yes @gatecat , sounds sensible to me. Can you rebase now software-rework has landed?
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Rebasing ended up a bit more complex than expected, but with ChipFlow/chipflow-lib#143, I think this should now be working
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Comment threadpicosoc_verilog/design/software/doit_build.py
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don't think this should be necessary now?
if the chipflow-lib impl doesnt do something you need, lets fix that
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It would be a ton of work to get software building working with Verilog, and I don't think everyone is even going to want this
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fair enough, see other comment..
Comment threadpicosoc_verilog/design/software/main.c
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Should the flashio/cmd_read_*/set_flash parts here be in the QSPIFlash driver?

Maybe fix up chipflow-lib if drivers need a way to put stuff in start.S?
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The picosoc qspi flash core isn't compatible with the one in chipflow-digital-ip so different drivers is needed
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ah, i see. this is fine for now then i guess, as you're overriding software build. We should have a bit of a session on making sure we can have design specific drivers work alongside imported drivers.
Comment threadpicosoc_verilog/design/software/main.c
}

void print_dec(uint32_t v)
{
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Why not something like:

do // run at least once to print 0

{

d = x % 10;

stack[sp++] = d + '0'; // push

x /= 10;

} while (x);
?
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I don't know, this was just taken from claire's picosoc code as-is
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how odd... Maybe note its origin in a comment?
Comment threadpicosoc_verilog/design/design.py

Comment on lines

+50
 to 
+63

 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

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any progress on this?
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Also seems this is using the long-deprecated PinSignature?? Please check you're working against a current chipflow-lib
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Hm, where is that, I thought I moved to using all the predefined signatures in chipflow-lib so sim auto-generation works, but maybe some old code got left in by mistake...
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I also don't touch pyproject.toml or pdm.lock in this PR so CI (where the tests pass, only the known issue of minimal timing out in the cloud builder causes a failure) should be using latest chipflow-lib already
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Maybe my local branch got messed up somehow, let me check it!
@gatecat@robtaylor
Adding a Verilog example using PicoSoC
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Signed-off-by: gatecat <gatecat@ds0.me>
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, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Auto-enable theater mode on YouTube\n(function() {\n function tryTheater() {\n var btn = document.querySelector('button[aria-label=\"Theater mode\"], ytd-player #player button[title=\"Theater mode\"]');\n if (btn && !btn.classList.contains('activated')) {\n btn.click();\n }\n }\n \n // Try immediately\n tryTheater();\n \n // Try after navigation (SPA)\n var lastUrl = location.href;\n setInterval(function() {\n if (location.href !== lastUrl) {\n lastUrl = location.href;\n setTimeout(tryTheater, 500);\n }\n }, 1000);\n \n // Also try on player load\n var observer = new MutationObserver(tryTheater);\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "YouTube Theater Mode Default");
}
} catch(__e) { console.warn('[Userscript:YouTube Theater Mode Default]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
Adding a Verilog example using PicoSoC - #39
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gatecat wants to merge 1 commit into
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Adding a Verilog example using PicoSoC#39
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@gatecat
@gatecatgatecat
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May 14, 2025•

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Everything else is ready for review, although I have a couple of questions:
  • should this be in this repo at all, or a different one?
  • should the top level wrapper still use amaranth-orchard pin signatures, as it does now, or is it clearer if it defines the pin signatures in the wrapper too (e.g. as an example for people who want to wrap Verilog with other types of IO)
@gatecat
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I think it belongs here. Defining the iopins here is better as well.
Let's not add a makefile - it was removed from the others.

Trying to keep things as windows compatible as we can, though still need to test.
@gatecat
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Let's not add a makefile - it was removed from the others.
Seems like it wasn't? e.g. https://github.com/ChipFlow/chipflow-examples/blob/main/mcu_soc/Makefile
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Hopefully once ChipFlow/chipflow-lib#129 is in this is ready to go!
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Comment threadpicosoc_verilog/design/design.py

Comment on lines

+50
 to 
+63

 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

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Just wondering, could we have a chipflow.toml section to include external code, or maybe use a seperate toml file for defining the import?
@robtaylorrobtaylorOct 10, 2025

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any progress on this?
Comment threadpicosoc_verilog/design/design.py

Comment on lines

+65
 to 
+93

 # Clock and reset
 i_clk=ClockSignal(),
 i_resetn=~ResetSignal(),

 # UART
 o_ser_tx=self.uart_0.tx.o,
 i_ser_rx=self.uart_0.rx.i,

 # SPI flash
 o_flash_csb=self.flash.csn.o,
 o_flash_clk=self.flash.clk.o,

 o_flash_io0_oe=self.flash.d.oe[0],
 o_flash_io1_oe=self.flash.d.oe[1],
 o_flash_io2_oe=self.flash.d.oe[2],
 o_flash_io3_oe=self.flash.d.oe[3],

 o_flash_io0_do=self.flash.d.o[0],
 o_flash_io1_do=self.flash.d.o[1],
 o_flash_io2_do=self.flash.d.o[2],
 o_flash_io3_do=self.flash.d.o[3],

 i_flash_io0_di=self.flash.d.i[0],
 i_flash_io1_di=self.flash.d.i[1],
 i_flash_io2_di=self.flash.d.i[2],
 i_flash_io3_di=self.flash.d.i[3],

 # LEDs
 o_leds=self.gpio_0.gpio.o
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Again, might be something worth putting in a toml description?
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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
@robtaylor
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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
Yes @gatecat , sounds sensible to me. Can you rebase now software-rework has landed?
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Rebasing ended up a bit more complex than expected, but with ChipFlow/chipflow-lib#143, I think this should now be working
robtaylor
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Comment threadpicosoc_verilog/design/software/doit_build.py
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don't think this should be necessary now?
if the chipflow-lib impl doesnt do something you need, lets fix that
@gatecatgatecatOct 10, 2025

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It would be a ton of work to get software building working with Verilog, and I don't think everyone is even going to want this
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fair enough, see other comment..
Comment threadpicosoc_verilog/design/software/main.c
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Should the flashio/cmd_read_*/set_flash parts here be in the QSPIFlash driver?

Maybe fix up chipflow-lib if drivers need a way to put stuff in start.S?
@gatecatgatecatOct 10, 2025

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The picosoc qspi flash core isn't compatible with the one in chipflow-digital-ip so different drivers is needed
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ah, i see. this is fine for now then i guess, as you're overriding software build. We should have a bit of a session on making sure we can have design specific drivers work alongside imported drivers.
Comment threadpicosoc_verilog/design/software/main.c
}

void print_dec(uint32_t v)
{
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Why not something like:

do // run at least once to print 0

{

d = x % 10;

stack[sp++] = d + '0'; // push

x /= 10;

} while (x);
?
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I don't know, this was just taken from claire's picosoc code as-is
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how odd... Maybe note its origin in a comment?
Comment threadpicosoc_verilog/design/design.py

Comment on lines

+50
 to 
+63

 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

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any progress on this?
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Also seems this is using the long-deprecated PinSignature?? Please check you're working against a current chipflow-lib
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Hm, where is that, I thought I moved to using all the predefined signatures in chipflow-lib so sim auto-generation works, but maybe some old code got left in by mistake...
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I also don't touch pyproject.toml or pdm.lock in this PR so CI (where the tests pass, only the known issue of minimal timing out in the cloud builder causes a failure) should be using latest chipflow-lib already
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Maybe my local branch got messed up somehow, let me check it!
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Adding a Verilog example using PicoSoC - #39
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Everything else is ready for review, although I have a couple of questions:
  • should this be in this repo at all, or a different one?
  • should the top level wrapper still use amaranth-orchard pin signatures, as it does now, or is it clearer if it defines the pin signatures in the wrapper too (e.g. as an example for people who want to wrap Verilog with other types of IO)
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I think it belongs here. Defining the iopins here is better as well.
Let's not add a makefile - it was removed from the others.

Trying to keep things as windows compatible as we can, though still need to test.
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Let's not add a makefile - it was removed from the others.
Seems like it wasn't? e.g. https://github.com/ChipFlow/chipflow-examples/blob/main/mcu_soc/Makefile
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Hopefully once ChipFlow/chipflow-lib#129 is in this is ready to go!
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Comment threadpicosoc_verilog/design/design.py

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+63

 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

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Just wondering, could we have a chipflow.toml section to include external code, or maybe use a seperate toml file for defining the import?
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any progress on this?
Comment threadpicosoc_verilog/design/design.py

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+65
 to 
+93

 # Clock and reset
 i_clk=ClockSignal(),
 i_resetn=~ResetSignal(),

 # UART
 o_ser_tx=self.uart_0.tx.o,
 i_ser_rx=self.uart_0.rx.i,

 # SPI flash
 o_flash_csb=self.flash.csn.o,
 o_flash_clk=self.flash.clk.o,

 o_flash_io0_oe=self.flash.d.oe[0],
 o_flash_io1_oe=self.flash.d.oe[1],
 o_flash_io2_oe=self.flash.d.oe[2],
 o_flash_io3_oe=self.flash.d.oe[3],

 o_flash_io0_do=self.flash.d.o[0],
 o_flash_io1_do=self.flash.d.o[1],
 o_flash_io2_do=self.flash.d.o[2],
 o_flash_io3_do=self.flash.d.o[3],

 i_flash_io0_di=self.flash.d.i[0],
 i_flash_io1_di=self.flash.d.i[1],
 i_flash_io2_di=self.flash.d.i[2],
 i_flash_io3_di=self.flash.d.i[3],

 # LEDs
 o_leds=self.gpio_0.gpio.o
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Again, might be something worth putting in a toml description?
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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
Yes @gatecat , sounds sensible to me. Can you rebase now software-rework has landed?
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Rebasing ended up a bit more complex than expected, but with ChipFlow/chipflow-lib#143, I think this should now be working
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Comment threadpicosoc_verilog/design/software/doit_build.py
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don't think this should be necessary now?
if the chipflow-lib impl doesnt do something you need, lets fix that
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It would be a ton of work to get software building working with Verilog, and I don't think everyone is even going to want this
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fair enough, see other comment..
Comment threadpicosoc_verilog/design/software/main.c
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Should the flashio/cmd_read_*/set_flash parts here be in the QSPIFlash driver?

Maybe fix up chipflow-lib if drivers need a way to put stuff in start.S?
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The picosoc qspi flash core isn't compatible with the one in chipflow-digital-ip so different drivers is needed
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ah, i see. this is fine for now then i guess, as you're overriding software build. We should have a bit of a session on making sure we can have design specific drivers work alongside imported drivers.
Comment threadpicosoc_verilog/design/software/main.c
}

void print_dec(uint32_t v)
{
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Why not something like:

do // run at least once to print 0

{

d = x % 10;

stack[sp++] = d + '0'; // push

x /= 10;

} while (x);
?
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I don't know, this was just taken from claire's picosoc code as-is
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how odd... Maybe note its origin in a comment?
Comment threadpicosoc_verilog/design/design.py

Comment on lines

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+63

 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

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any progress on this?
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Also seems this is using the long-deprecated PinSignature?? Please check you're working against a current chipflow-lib
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Hm, where is that, I thought I moved to using all the predefined signatures in chipflow-lib so sim auto-generation works, but maybe some old code got left in by mistake...
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I also don't touch pyproject.toml or pdm.lock in this PR so CI (where the tests pass, only the known issue of minimal timing out in the cloud builder causes a failure) should be using latest chipflow-lib already
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Maybe my local branch got messed up somehow, let me check it!
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Adding a Verilog example using PicoSoC - #39
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Everything else is ready for review, although I have a couple of questions:
  • should this be in this repo at all, or a different one?
  • should the top level wrapper still use amaranth-orchard pin signatures, as it does now, or is it clearer if it defines the pin signatures in the wrapper too (e.g. as an example for people who want to wrap Verilog with other types of IO)
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I think it belongs here. Defining the iopins here is better as well.
Let's not add a makefile - it was removed from the others.

Trying to keep things as windows compatible as we can, though still need to test.
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Let's not add a makefile - it was removed from the others.
Seems like it wasn't? e.g. https://github.com/ChipFlow/chipflow-examples/blob/main/mcu_soc/Makefile
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Hopefully once ChipFlow/chipflow-lib#129 is in this is ready to go!
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Comment threadpicosoc_verilog/design/design.py

Comment on lines

+50
 to 
+63

 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

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Just wondering, could we have a chipflow.toml section to include external code, or maybe use a seperate toml file for defining the import?
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any progress on this?
Comment threadpicosoc_verilog/design/design.py

Comment on lines

+65
 to 
+93

 # Clock and reset
 i_clk=ClockSignal(),
 i_resetn=~ResetSignal(),

 # UART
 o_ser_tx=self.uart_0.tx.o,
 i_ser_rx=self.uart_0.rx.i,

 # SPI flash
 o_flash_csb=self.flash.csn.o,
 o_flash_clk=self.flash.clk.o,

 o_flash_io0_oe=self.flash.d.oe[0],
 o_flash_io1_oe=self.flash.d.oe[1],
 o_flash_io2_oe=self.flash.d.oe[2],
 o_flash_io3_oe=self.flash.d.oe[3],

 o_flash_io0_do=self.flash.d.o[0],
 o_flash_io1_do=self.flash.d.o[1],
 o_flash_io2_do=self.flash.d.o[2],
 o_flash_io3_do=self.flash.d.o[3],

 i_flash_io0_di=self.flash.d.i[0],
 i_flash_io1_di=self.flash.d.i[1],
 i_flash_io2_di=self.flash.d.i[2],
 i_flash_io3_di=self.flash.d.i[3],

 # LEDs
 o_leds=self.gpio_0.gpio.o
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Again, might be something worth putting in a toml description?
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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
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@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?
Yes @gatecat , sounds sensible to me. Can you rebase now software-rework has landed?
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Rebasing ended up a bit more complex than expected, but with ChipFlow/chipflow-lib#143, I think this should now be working
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Comment threadpicosoc_verilog/design/software/doit_build.py
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don't think this should be necessary now?
if the chipflow-lib impl doesnt do something you need, lets fix that
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It would be a ton of work to get software building working with Verilog, and I don't think everyone is even going to want this
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fair enough, see other comment..
Comment threadpicosoc_verilog/design/software/main.c
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Should the flashio/cmd_read_*/set_flash parts here be in the QSPIFlash driver?

Maybe fix up chipflow-lib if drivers need a way to put stuff in start.S?
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The picosoc qspi flash core isn't compatible with the one in chipflow-digital-ip so different drivers is needed
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ah, i see. this is fine for now then i guess, as you're overriding software build. We should have a bit of a session on making sure we can have design specific drivers work alongside imported drivers.
Comment threadpicosoc_verilog/design/software/main.c
}

void print_dec(uint32_t v)
{
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Why not something like:

do // run at least once to print 0

{

d = x % 10;

stack[sp++] = d + '0'; // push

x /= 10;

} while (x);
?
@gatecatgatecatOct 10, 2025

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I don't know, this was just taken from claire's picosoc code as-is
@robtaylorrobtaylorOct 16, 2025

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how odd... Maybe note its origin in a comment?
Comment threadpicosoc_verilog/design/design.py

Comment on lines

+50
 to 
+63

 base = os.path.dirname(__file__)

 verilog_sources = [
 f"{base}/picosoc_asic_top.v",
 f"{base}/picorv32/picosoc/spimemio.v",
 f"{base}/picorv32/picosoc/simpleuart.v",
 f"{base}/picorv32/picosoc/picosoc.v",
 f"{base}/picorv32/picorv32.v",
 ]

 for verilog_file in verilog_sources:
 with open(verilog_file, 'r') as f:
 platform.add_file(verilog_file, f)

@robtaylorrobtaylorOct 10, 2025

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any progress on this?
@robtaylor
robtaylor
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Oct 16, 2025

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Also seems this is using the long-deprecated PinSignature?? Please check you're working against a current chipflow-lib
@gatecat
gatecat
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Oct 16, 2025

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Hm, where is that, I thought I moved to using all the predefined signatures in chipflow-lib so sim auto-generation works, but maybe some old code got left in by mistake...
@gatecat
gatecat
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Oct 16, 2025

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I also don't touch pyproject.toml or pdm.lock in this PR so CI (where the tests pass, only the known issue of minimal timing out in the cloud builder causes a failure) should be using latest chipflow-lib already
@robtaylor
robtaylor
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Oct 16, 2025

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Maybe my local branch got messed up somehow, let me check it!
@gatecat@robtaylor
Adding a Verilog example using PicoSoC
ab4addc
Signed-off-by: gatecat <gatecat@ds0.me>
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