feat: c64-lib-contract alignment + libs/nistcurves v0.3.0 + libs/x25519 v0.6.0 - #55
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…19 v0.6.0 Aligns c64-https with c64-lib-contract v0.2.0 (published 2026-05-20) and the new library releases: * libs/nistcurves: 90830c9 -> v0.3.0 (post-#40 minimal-archive build targets, SPEC s1-s6 + s8.1 adopted, LIB_ABI_VERSION exported) * libs/x25519: 47c0ad21 (v0.4.0) -> v0.6.0 (SPEC s1-s5 + s8.1 adopted, REU bank-2 drop, RAM-reclaim, lib-x25519-1764 minimal variant) c64-https consumer-side changes: * UCI cfg restructure (W1): split monolithic 24 KB CRYPTO_RESIDENT into 16 KB CRYPTO_HOT (code+rodata, file-backed) + 8 KB CRYPTO_COLD_SHADOW ($A000-$BFFF, BSS under banked-off BASIC ROM). Routes new LIB_NISTCURVES_* segments per their cold/hot profile. Closes the segment-straddles-$A000 boot-zero-wipe regression that caused Test 3a to time out at 30 s. * Integration scripts collapse: build_nistcurves_p{256,384}.sh shed ~636 lines of sed-strip shell in favor of make -C libs/nistcurves lib-p{256,384}-verify. build_x25519.sh adapted to consume v0.6.0's .exportzp ZP config + REU bank --asm-define (plus SPEC s8.1 LIB_SHARED_SQTAB_BASE=$BC00 + SHARED_SQTAB_INIT=1). build_nistcurves_p256_bin.sh new -- builds the P-256 verify overlay .bin for EMBED_P256_OVERLAY=1 path. * Overlay-swap infrastructure: src/crypto/shared/crypto_swap.s extended with crypto_swap_to_x25519, crypto_swap_to_p256_verify, crypto_overlay_call. New overlay_ids.inc for canonical OV_* equates. src/boot.s reu_p384_overlay_init extended to stash X25519 + P-256 verify images. New entry points are unused in default build (W1's hot path stays unchanged) -- they're plumbing for future cold-path routing. * BSS_TAIL segment: small new segment for src/data.s::tls_rec_buf (548 B) + src/der_decode.s::cert_buf (1536 B) routed where each backend has room. Verified: * make BACKEND=uci (two-pass bootstrap): 62,977 B PRG (byte-identical to pre-bump baseline) * tools/test_x509.py: 11/11 PASS * tools/uci/test_https_local.py (U64E hw): PASS at 82.1 s (vs 81.8 s CLAUDE.md baseline -- +0.3 s noise) Known limitations (tracked): * BACKEND=ip65 build: 1662 B over in CRYPTO_COLD_SHADOW. Blocked on c64-nist-curves#54 (lib-p256-verify BSS slim -- would close ~261 B) + likely src-side cert-parse streaming or further library asks. * make BACKEND=uci USE_X25519_SIBLING=1: 364 B over in CRYPTO_HOT (was 415 B pre-bump; x25519 v0.6.0 reclaimed 51 B). Will likely close with c64-nist-curves#54. * Default UCI build is the production target; both above paths are non-default flags. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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…te (#56) CLAUDE.md was partially updated during the session that produced PRs #51-#55; several sections survived with pre-bump claims that no longer match reality. This commit refreshes them in one pass: - Crypto ABI: bump x25519 sibling pin v0.4.0 -> v0.6.0; mark P-256 as c64-lib-contract SPEC-aligned with the make -C libs/<X> lib-VARIANT integration pattern. - MEMORY requirements: rename CRYPTO -> CRYPTO_HOT (UCI) / CRYPTO_RESIDENT (ip65) per the W1 hot/cold split; cross-link c64-lib-contract repo + docs/library-ingestion-architecture.md. - Build vars: document USE_X25519_SIBLING + EMBED_P256_OVERLAY. - UCI Memory layout: collapse to a pointer at the post-W1 table below. - Known issues: rewrite the X25519 sibling block for v0.6.0 + the post-W1 split; replace MemoryPolicy note with the centralized VICE helper (tools/_vice_helpers.py::default_vice_config). - ECDSA P-256 wall-clock: update to 82.1 s under v0.3.0 (was 86.7 s under v0.2.0); drop the v0.2.0-era defensive-init footnote. - Memory layout: replace pre-W1 monolithic CRYPTO table with the full UCI + ip65 post-W1 layout; document the ip65 CRYPTO_COLD_SHADOW 1,662 B overflow tracked at c64-nist-curves#54. docs/library-ingestion-architecture.md gets a "Status as of 2026-05-23" appendix snapshotting which §3 library-side issues and §4 c64-https-side work items landed via PRs #51-#55 vs. are still in-flight (Task #12 / P-384 wall-clock / CI bot). No source / cfg / integration script / submodule changes. Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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…te (#57) CLAUDE.md was partially updated during the session that produced PRs #51-#55; several sections survived with pre-bump claims that no longer match reality. This commit refreshes them in one pass: - Crypto ABI: bump x25519 sibling pin v0.4.0 -> v0.6.0; mark P-256 as c64-lib-contract SPEC-aligned with the make -C libs/<X> lib-VARIANT integration pattern. - MEMORY requirements: rename CRYPTO -> CRYPTO_HOT (UCI) / CRYPTO_RESIDENT (ip65) per the W1 hot/cold split; cross-link c64-lib-contract repo + docs/library-ingestion-architecture.md. - Build vars: document USE_X25519_SIBLING + EMBED_P256_OVERLAY. - UCI Memory layout: collapse to a pointer at the post-W1 table below. - Known issues: rewrite the X25519 sibling block for v0.6.0 + the post-W1 split; replace MemoryPolicy note with the centralized VICE helper (tools/_vice_helpers.py::default_vice_config). - ECDSA P-256 wall-clock: update to 82.1 s under v0.3.0 (was 86.7 s under v0.2.0); drop the v0.2.0-era defensive-init footnote. - Memory layout: replace pre-W1 monolithic CRYPTO table with the full UCI + ip65 post-W1 layout; document the ip65 CRYPTO_COLD_SHADOW 1,662 B overflow tracked at c64-nist-curves#54. docs/library-ingestion-architecture.md gets a "Status as of 2026-05-23" appendix snapshotting which §3 library-side issues and §4 c64-https-side work items landed via PRs #51-#55 vs. are still in-flight (Task #12 / P-384 wall-clock / CI bot). No source / cfg / integration script / submodule changes. Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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* docs: refresh CLAUDE.md + ingestion plan for PR #46/#51-55 merged state CLAUDE.md was partially updated during the session that produced PRs #51-#55; several sections survived with pre-bump claims that no longer match reality. This commit refreshes them in one pass: - Crypto ABI: bump x25519 sibling pin v0.4.0 -> v0.6.0; mark P-256 as c64-lib-contract SPEC-aligned with the make -C libs/<X> lib-VARIANT integration pattern. - MEMORY requirements: rename CRYPTO -> CRYPTO_HOT (UCI) / CRYPTO_RESIDENT (ip65) per the W1 hot/cold split; cross-link c64-lib-contract repo + docs/library-ingestion-architecture.md. - Build vars: document USE_X25519_SIBLING + EMBED_P256_OVERLAY. - UCI Memory layout: collapse to a pointer at the post-W1 table below. - Known issues: rewrite the X25519 sibling block for v0.6.0 + the post-W1 split; replace MemoryPolicy note with the centralized VICE helper (tools/_vice_helpers.py::default_vice_config). - ECDSA P-256 wall-clock: update to 82.1 s under v0.3.0 (was 86.7 s under v0.2.0); drop the v0.2.0-era defensive-init footnote. - Memory layout: replace pre-W1 monolithic CRYPTO table with the full UCI + ip65 post-W1 layout; document the ip65 CRYPTO_COLD_SHADOW 1,662 B overflow tracked at c64-nist-curves#54. docs/library-ingestion-architecture.md gets a "Status as of 2026-05-23" appendix snapshotting which §3 library-side issues and §4 c64-https-side work items landed via PRs #51-#55 vs. are still in-flight (Task #12 / P-384 wall-clock / CI bot). No source / cfg / integration script / submodule changes. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> * feat(uci): C64 Ultimate support — 64 MHz e2e + WiFi DHCP + fence retune (#58) * fix(uci): widen uci_fence to keep 35% margin at 64 MHz The C64 Ultimate tops out at 64 MHz, where the old 2525-cycle fence (INNER=100, tuned for 48 MHz) shrinks to ~39.5 us — only ~4% over the FPGA's ~38 us floor. Bump UCI_FENCE_INNER to 131 (~3300 cycles): 51.6 us at 64 MHz (35.7% margin), 68.8 us at 48 MHz, ~3.3 ms at 1 MHz. Still negligible for networking at every speed. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01UZmMaxyyykvYbCvJAc4QVW * feat(uci): interface-fallback DHCP acquire for C64 Ultimate WiFi The C64 Ultimate has Ethernet AND WiFi; GET_IPADDR(iface=0) returns 0.0.0.0 when the box is on WiFi, which the old single-shot net_dhcp_acquire surfaced as DHCP FAILED (UCI_ERR_NO_IP). Probe interface indices 0..3 and take the first non-zero lease; clean up (drain + ack) after a CMD_FAILED probe so the next one starts from idle. Clear net_last_error on success so no-lease residue from earlier probes doesn't sit next to a good acquire. Costs ~38 B in NET_CODE — boundary with NET_BSS_TAIL shifted by $40 ($1B26 -> $1B66); NET_BSS_TAIL occupancy is $625 so $75 slack remains. Verified on C64 Ultimate firmware 1.1.0 (WiFi): phase2_check PASS, IP acquired on iface 1. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01UZmMaxyyykvYbCvJAc4QVW * fix(uci): retune uci_fence for C64 Ultimate burst floor The C64U (firmware 1.1.0, core 1.49) needs more inter-access time than the U64E's empirical ~38 us, and only under sustained CMD_DATA bursts: at 51.6 us spacing (INNER=131 @ 64 MHz) GET_IPADDR works but TCP_CONNECT's ~15-byte hostname push is silently lost (UCI_ERR_NO_SOCKET, no SYN ever leaves the box). Floor bracketed at 64 MHz: 51.6 us FAIL / 62.9 us PASS / 100 us PASS. Ship INNER=217 (5450 cycles = 85.2 us @ 64 MHz) for 35% margin over the worst-case floor; 113.5 us @ 48 MHz, ~5.5 ms @ 1 MHz — negligible for networking on both devices. E2e verified on C64U: 64 MHz PASS (64.7 s), 48 MHz PASS (73.0 s). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01UZmMaxyyykvYbCvJAc4QVW * test(uci): set turbo before boot — C64U runtime-switch quirk On the C64 Ultimate, a REST config CPU-speed change while the PRG is running can glitch the UCI bridge so the next pushed command is silently lost — reproduced 2x as UCI_ERR_NO_SOCKET on the first TCP_CONNECT after a 1->64 MHz switch, even with a 100 us fence (1->48 happened to survive). Move set_turbo_mhz before reset/run_prg so the machine boots at target speed and never switches mid-session; also makes boot speed deterministic instead of inheriting the previous run's config. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01UZmMaxyyykvYbCvJAc4QVW * docs: C64 Ultimate notes + 48/64 MHz benchmarks New bench device: C64 Ultimate Starlight (10.53.21.158, fw 1.1.0, core 1.49, NTSC, WiFi). Documents the 64 MHz speed enum, the runtime speed-switch quirk, the wider fence floor, multi-interface GET_IPADDR, REU-disabled default + set_reu() incompatibility, and the new P-256 e2e numbers: 73.0 s @ 48 MHz, 64.7 s @ 64 MHz. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01UZmMaxyyykvYbCvJAc4QVW * bench+docs: 48/64 MHz verify scaling analysis — REU DMA is the wall bench_ecdsa_u64e.py: the post-W1 MemoryPolicy blocks the bench's DMA writes of vector inputs into CRYPTO_BSS (now in CRYPTO_COLD_SHADOW); pass override= with a reason instead of widening the policy. Measured on C64U: ecdsa_verify_256 53.8 s @ 48 MHz / 47.4 s @ 64 MHz. T(f) = D + C/f fits both e2e and verify pairs to 0.1 s: verify D = 28.4 s speed-invariant vs C = 1.22 Gcycles CPU-scaled. D matches fp_mul's REU row-fetch volume (~27 MB/verify) at the stock ~1 MB/s DMA rate that turbo does not scale (consistent with the 16 ms overlay-swap datapoint). e2e adds ~11.4 s of UCI/network D. Conclusion documented in CLAUDE.md: >48 MHz clocks are mostly wasted on this fp_mul; the fix is library-side. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01UZmMaxyyykvYbCvJAc4QVW --------- Co-authored-by: Claude Fable 5 <noreply@anthropic.com> --------- Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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…s handshake @64 MHz (#60) * feat(crypto): nistcurves v0.5.0 + USE_NISTCURVES_ONCHIP turbo profile Bump libs/nistcurves v0.3.0 -> v0.5.0 and wire the FP_ONCHIP_MUL turbo profile (upstream issue #69) behind USE_NISTCURVES_ONCHIP=1: - wrapper: profile arg (reu|onchip); dynamic member list (v0.5.0 renamed/added archive members); onchip mode rebuilds mul_8x8_onchip.o with the SHARED_* consumer defines + LIB_SHARED_SQTAB_BASE=$BC00 via a generated glue TU (upstream's SHARED_CT_MUL_8X8 x FP_ONCHIP_MUL combo lacks .imports — composition bridge, no libs/ source patch) - poly1305.s: under the flag, provide the c64-lib-contract §8.3 canonical ct_mul_8x8 (+ SMC bake sites) with the legacy A=a/X=b mul_8x8 kept as a thin shim; default build byte-path unchanged - data.s: yield sqtab_lo/hi to the lib's $BC00 equates under the flag (aligned same-size placeholder keeps TABLES_BSS layout; post-link Makefile check asserts sqtab_reserved==$BC00) - boot.s: skip the ~128 KB reu_mul_init population + yield the reu_fetch_mul_row export under the flag (onchip verify issues no REU row DMA; boot obligation shrinks to sqtab_init) - cfg/uci: LIB_NISTCURVES_MUL_CODE -> CRYPTO_OVERLAY (onchip fp256 growth overflows CRYPTO_HOT by 59 B otherwise); Makefile guards the flag against X25519_SIBLING + both overlay-embed flags Correctness: VICE KAT oracle 3/3 PASS against the onchip UCI PRG (CAVP SigVer vectors). Default UCI build: byte-identical behavior, 0 warnings. KNOWN: plain ip65 does not link at either pin (BSS overflows CRYPTO_COLD_SHADOW by 1662 B @ v0.3.0, 1406 B @ v0.5.0) — pre-existing on master since PR #55, improved-but-not-fixed by this bump; tracked at c64-nist-curves#54. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01UZmMaxyyykvYbCvJAc4QVW * fix(boot): retain reu_mul_init under onchip profile — C64U bridge quirk Controlled A/B on C64U hardware (2026-07-20): an onchip-profile boot that issues no REU DMA loses the first UCI TCP_CONNECT at the FPGA bridge (command accepted, no error bit, DATA_AV never asserts, no SYN on the wire) — 0/8 e2e attempts across the day. The identical build with reu_mul_init retained passes 3/3 (47.0-47.8 s @ 64 MHz), and an interleaved re-run of the REU-quiet build still fails 0/2 in the same window. Boot-time REU traffic evidently settles shared expansion-I/O state the UCI bridge depends on. Cost: ~1 s of boot; REU banks 0/1 population is otherwise unused under the onchip profile. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01UZmMaxyyykvYbCvJAc4QVW * docs: turbo-profile campaign results — crossover ~34 MHz, e2e 47.5 s @64 Full 4-point clock sweeps on the C64U for v0.3.0-REU / v0.5.0-REU / v0.5.0-onchip: REU floor is ~42 s (supersedes the ill-conditioned 2-point 28.4 s figure), onchip floor 2.5 s, measured crossover ~34 MHz with an in-band bracket at 32 MHz. HTTPS e2e: 59.9 s @48 / 47.5 s @64 under the onchip profile — first sub-50 s handshake. Adds the USE_NISTCURVES_ONCHIP build flag docs and the C64U REU-quiet-boot connect quirk (c64-test-harness#137). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01UZmMaxyyykvYbCvJAc4QVW --------- Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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Summary
Aligns c64-https with c64-lib-contract v0.2.0 (published 2026-05-20) and the new library releases:
LIB_ABI_VERSIONexported)lib-x25519-1764minimal variant)c64-https consumer-side changes:
LIB_NISTCURVES_*segments per their cold/hot profile. Closes the segment-straddles-$A000 boot-zero-wipe regression that caused Test 3a to time out at 30 s.build_nistcurves_p{256,384}.shshed ~636 lines of sed-strip shell in favor ofmake -C libs/nistcurves lib-p{256,384}-verify.build_x25519.shadapted to consume v0.6.0's.exportzpZP config + REU bank--asm-define(plus SPEC s8.1LIB_SHARED_SQTAB_BASE=$BC00+SHARED_SQTAB_INIT=1).build_nistcurves_p256_bin.shnew -- builds the P-256 verify overlay .bin for EMBED_P256_OVERLAY=1 path.src/crypto/shared/crypto_swap.sextended withcrypto_swap_to_x25519,crypto_swap_to_p256_verify,crypto_overlay_call. Newoverlay_ids.incfor canonical OV_* equates.src/boot.sreu_p384_overlay_initextended to stash X25519 + P-256 verify images. New entry points are unused in default build (W1's hot path stays unchanged) -- they're plumbing for future cold-path routing.src/data.s::tls_rec_buf(548 B) +src/der_decode.s::cert_buf(1536 B) routed where each backend has room.Note: CLAUDE.md refresh in the session-snapshot is already on origin/master via the baseline catchup (PR #51), so it is intentionally not included here.
Verified
make BACKEND=uci(two-pass bootstrap): 62,977 B PRG (byte-identical to pre-bump baseline)tools/test_x509.py: 11/11 PASS (Test 3a was timing out 30 s on the pre-cfg-fix tree)tools/uci/test_https_local.py(U64E hw): PASS at 82.1 s (vs 81.8 s CLAUDE.md baseline -- +0.3 s noise)Known limitations (tracked)
BACKEND=ip65build: 1662 B over in CRYPTO_COLD_SHADOW. Blocked on c64-nist-curves#54 (lib-p256-verify BSS slim -- would close ~261 B) + likely src-side cert-parse streaming or further library asks.make BACKEND=uci USE_X25519_SIBLING=1: 364 B over in CRYPTO_HOT (was 415 B pre-bump; x25519 v0.6.0 reclaimed 51 B). Will likely close with c64-nist-curves#54.Test plan
make clean && make BACKEND=uci USE_OVERLAY_P384_EMBED=0 USE_OVERLAY_P256_EMBED=0 && make BACKEND=uciclean + 62977 Bpython3 tools/test_x509.py11/11 PASSU64_HOST=10.43.23.81 python3 tools/uci/test_https_local.pyPASS at ~82 sGenerated with Claude Code