Actions: LessComplexity/mapal
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72 workflow runs
perf(sched): chained bulk ops were never parallel
CI
#72:
Commit c78c9af
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LessComplexity
docs(handoff): record the results-vs-emission byte-identity split
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#71:
Commit 680ce44
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LessComplexity
docs(s44-s47): close the session — log, handoff, status roll-up
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#70:
Commit 3134a5c
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LessComplexity
fix(llvm): decline non-power-of-two widths — they lost 1.75x
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#68:
Commit 8d322ca
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LessComplexity
docs(readme): results section is results
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#67:
Commit fe69bf1
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LessComplexity
fix(llvm): detect the vector ISA too, not just the caches
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#66:
Commit b4af6a0
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LessComplexity
docs(readme): M4 shape rows re-measured on a detecting build
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#65:
Commit 2ac75a0
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LessComplexity
feat(llvm): detect the machine by default
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#64:
Commit 233d7eb
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LessComplexity
docs(readme): transpose fix needs a machine-aware target — say so
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#63:
Commit 4fe9e8a
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LessComplexity
feat(llvm,ir): the cache-conflict fix deduces itself — no flag
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#62:
Commit d52c136
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LessComplexity
perf(llvm): transpose was fighting the cache, not the bandwidth — 1.9…
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#61:
Commit 1877b73
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LessComplexity
fix(bench): emit_sweep_ab preflight — reject the wrong emit binary
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#60:
Commit 7eb4212
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LessComplexity
docs(s43): close the session — reconcile the handoff after the merge
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#59:
Commit 6d6302c
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LessComplexity
docs(readme): "what is next" lists only what is next
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#58:
Commit aff5bde
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LessComplexity
docs: drop the NEON-leg follow-up; matmul ships SME
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#57:
Commit 9df8a65
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LessComplexity
perf(llvm): the B pack was serial — parallelize it, 1.381x threaded
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#56:
Commit 555d058
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LessComplexity
docs(s42): the SME gap is operand cache residency, worth ~1.79x
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#55:
Commit 0518e76
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LessComplexity
docs(session): close S41b; S42 opens on k-loop pipelining
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#54:
Commit 06ac50a
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LessComplexity
docs: complete the SME matmul tables to all four sizes, both widths
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#53:
Commit b8980ee
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LessComplexity
docs(perf): the threaded SME campaign, and the 4096 knee was misdiagn…
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#52:
Commit da4cd1d
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LessComplexity
perf(llvm): SME spends every ZA tile; numpy 1t gap 13.5x -> 1.62x
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#51:
Commit 62b63d2
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LessComplexity
feat(llvm): ARM SME tile realization; split func.rs; gate the geometr…
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#50:
Commit 7732a5f
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LessComplexity
feat(ir): guards gate the flow; arms own loops as units (S39+S40)
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#49:
Commit aaaa5dd
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LessComplexity