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Fix memory fence for ARM - #753

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aurianer wants to merge 4 commits into
NVIDIA:mainfrom
aurianer:fix_barrier_for_aarch64
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Fix memory fence for ARM#753
aurianer wants to merge 4 commits into
NVIDIA:mainfrom
aurianer:fix_barrier_for_aarch64

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@aurianer

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TransformerEngine doesn't compile for aarch64, this PR:

  • Conditionally use data memory barrier for ARM architecture.
  • Fix a redefinition error coming from gdrapi.h defining the GPU_PAGE_* macros and already included in userbuffers.h. This adds an explicit include (which is guarded and prevent redefinition) since the GPU_PAGE_* variables are used in this .cpp file.

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aurianerforce-pushed the fix_barrier_for_aarch64 branch from 5882c94 to 842dc17CompareApril 5, 2024 14:44

@timmoon10timmoon10 left a comment

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Overall LGTM

Comment threadtransformer_engine/pytorch/csrc/userbuffers/userbuffers-host.cpp Outdated
Comment threadtransformer_engine/pytorch/csrc/userbuffers/userbuffers-host.cpp Outdated
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/te-ci pytorch

@aurianer
aurianerforce-pushed the fix_barrier_for_aarch64 branch from 8a06c92 to df72d04CompareApril 8, 2024 13:37
@aurianer

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Out of curiosity, why is the sleep(1) needed? Would it make sense to use a memory barrier in assembly using the nop instruction (longer than _mm_mfence I believe)

henrique added a commit to henrique/TransformerEngine that referenced this pull request Apr 10, 2024
Comment threadtransformer_engine/pytorch/csrc/userbuffers/userbuffers-host.cpp Outdated
aurianerand others added 3 commits April 10, 2024 13:08
Signed-off-by: aurianer <aurianer@cscs.ch>
Signed-off-by: aurianer <aurianer@cscs.ch>
Signed-off-by: Tim Moon <4406448+timmoon10@users.noreply.github.com>
@aurianer
aurianerforce-pushed the fix_barrier_for_aarch64 branch from df72d04 to cf93f1bCompareApril 10, 2024 11:09
Signed-off-by: aurianer <aurianer@cscs.ch>
@aurianer
aurianerforce-pushed the fix_barrier_for_aarch64 branch from cf93f1b to a7d5357CompareApril 10, 2024 16:52
@timmoon10

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/te-ci pytorch

@aurianer

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closing in favour of #757

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4 participants

@aurianer@timmoon10@henrique@shamisp