PyFPGA

A Python package to use FPGA development tools programmatically.

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

Containers for FOSS tools

Shared resources (HDL and constraint files) between projects of the PyFPGA organization.

Proofs of concept about FPGA EDA tools.

A possible replacement for openflow, which would be ideally contributed to the SymbiFlow project

A Python library, and CLI utilities, which solves HDL-to-bitstream based on FOSS.