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Verilator testbench for ISA tests - #8

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SI-RISCV:masterfrom
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Verilator testbench for ISA tests#8
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@brabect1brabect1 commented Aug 7, 2018

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This pull requests adds a testbench and Makefile to run ISA tests against RTL with Verilator.

There are minor changes in RTL to make it work with Verilator. Minor changes also made in fpga and SDK Makefiles (these are not needed for the Verilator testbech).

Tomas Brabec-FG6B3Hand others added 4 commits July 31, 2018 15:01
Tomas Brabec-FG6B3H
Minor updates in Makefiles.
d0b189c
Changed FPGA build makefile to use e203 as a default CORE and did few minor enhancements.
Updated SDK makefile to let users re-define toolchain binaries names from environment. This shall help using different pre-compiled toolchains.
@brabect1
Added initial support for using Verilator with riscv ISA tests.
0ff7b1a
Testbench and Makefile added into a separate folder (originating from
the existing ISA tests testbench). Minor updates to Verilog code to let
it work with Verilator. Run with v3.924 and --trace enabled (without
--trace the simulation does not converge/end).
@brabect1
Created make targets for running ISA tests in a regression suite.
3da945e
Also added help target to the Makefile so that it becomes the default
one. Added README file with instructions and known limitations. Added
license statements (Apache 2.0).
@brabect1
Fixed instruction for building with older Verilator version.
21e71fb
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Verilator testbench for ISA tests by brabect1 · Pull Request #8 · SI-RISCV/e200_opensource · GitHub
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This repository was archived by the owner on Mar 24, 2021. It is now read-only.

Verilator testbench for ISA tests - #8
Open
brabect1 wants to merge 4 commits into
SI-RISCV:masterfrom 
brabect1:master
Open
Verilator testbench for ISA tests#8
brabect1 wants to merge 4 commits into
SI-RISCV:masterfrom 
brabect1:master
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@brabect1
@brabect1brabect1
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Aug 7, 2018

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This pull requests adds a testbench and Makefile to run ISA tests against RTL with Verilator.
There are minor changes in RTL to make it work with Verilator. Minor changes also made in fpga and SDK Makefiles (these are not needed for the Verilator testbech).
Tomas Brabec-FG6B3Hand others
added 4 commits
July 31, 2018 15:01
Tomas Brabec-FG6B3H
Minor updates in Makefiles.
d0b189c
Changed FPGA build makefile to use e203 as a default CORE and did few minor enhancements.
Updated SDK makefile to let users re-define toolchain binaries names from environment. This shall help using different pre-compiled toolchains.
@brabect1
Added initial support for using Verilator with riscv ISA tests.
0ff7b1a
Testbench and Makefile added into a separate folder (originating from
the existing ISA tests testbench). Minor updates to Verilog code to let
it work with Verilator. Run with v3.924 and --trace enabled (without
--trace the simulation does not converge/end).
@brabect1
Created make targets for running ISA tests in a regression suite.
3da945e
Also added help target to the Makefile so that it becomes the default
one. Added README file with instructions and known limitations. Added
license statements (Apache 2.0).
@brabect1
Fixed instruction for building with older Verilator version.
21e71fb
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, 'i');
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Verilator testbench for ISA tests by brabect1 · Pull Request #8 · SI-RISCV/e200_opensource · GitHub
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This repository was archived by the owner on Mar 24, 2021. It is now read-only.

Verilator testbench for ISA tests - #8
Open
brabect1 wants to merge 4 commits into
SI-RISCV:masterfrom 
brabect1:master
Open
Verilator testbench for ISA tests#8
brabect1 wants to merge 4 commits into
SI-RISCV:masterfrom 
brabect1:master
Conversation
@brabect1
@brabect1brabect1
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Aug 7, 2018

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This pull requests adds a testbench and Makefile to run ISA tests against RTL with Verilator.
There are minor changes in RTL to make it work with Verilator. Minor changes also made in fpga and SDK Makefiles (these are not needed for the Verilator testbech).
Tomas Brabec-FG6B3Hand others
added 4 commits
July 31, 2018 15:01
Tomas Brabec-FG6B3H
Minor updates in Makefiles.
d0b189c
Changed FPGA build makefile to use e203 as a default CORE and did few minor enhancements.
Updated SDK makefile to let users re-define toolchain binaries names from environment. This shall help using different pre-compiled toolchains.
@brabect1
Added initial support for using Verilator with riscv ISA tests.
0ff7b1a
Testbench and Makefile added into a separate folder (originating from
the existing ISA tests testbench). Minor updates to Verilog code to let
it work with Verilator. Run with v3.924 and --trace enabled (without
--trace the simulation does not converge/end).
@brabect1
Created make targets for running ISA tests in a regression suite.
3da945e
Also added help target to the Makefile so that it becomes the default
one. Added README file with instructions and known limitations. Added
license statements (Apache 2.0).
@brabect1
Fixed instruction for building with older Verilator version.
21e71fb
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Verilator testbench for ISA tests by brabect1 · Pull Request #8 · SI-RISCV/e200_opensource · GitHub
Skip to content

This repository was archived by the owner on Mar 24, 2021. It is now read-only.

Verilator testbench for ISA tests - #8
Open
brabect1 wants to merge 4 commits into
SI-RISCV:masterfrom 
brabect1:master
Open
Verilator testbench for ISA tests#8
brabect1 wants to merge 4 commits into
SI-RISCV:masterfrom 
brabect1:master
Conversation
@brabect1
@brabect1brabect1
commented
Aug 7, 2018

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This pull requests adds a testbench and Makefile to run ISA tests against RTL with Verilator.
There are minor changes in RTL to make it work with Verilator. Minor changes also made in fpga and SDK Makefiles (these are not needed for the Verilator testbech).
Tomas Brabec-FG6B3Hand others
added 4 commits
July 31, 2018 15:01
Tomas Brabec-FG6B3H
Minor updates in Makefiles.
d0b189c
Changed FPGA build makefile to use e203 as a default CORE and did few minor enhancements.
Updated SDK makefile to let users re-define toolchain binaries names from environment. This shall help using different pre-compiled toolchains.
@brabect1
Added initial support for using Verilator with riscv ISA tests.
0ff7b1a
Testbench and Makefile added into a separate folder (originating from
the existing ISA tests testbench). Minor updates to Verilog code to let
it work with Verilator. Run with v3.924 and --trace enabled (without
--trace the simulation does not converge/end).
@brabect1
Created make targets for running ISA tests in a regression suite.
3da945e
Also added help target to the Makefile so that it becomes the default
one. Added README file with instructions and known limitations. Added
license statements (Apache 2.0).
@brabect1
Fixed instruction for building with older Verilator version.
21e71fb
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, 'i');
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Verilator testbench for ISA tests by brabect1 · Pull Request #8 · SI-RISCV/e200_opensource · GitHub
Skip to content

This repository was archived by the owner on Mar 24, 2021. It is now read-only.

Verilator testbench for ISA tests - #8
Open
brabect1 wants to merge 4 commits into
SI-RISCV:masterfrom 
brabect1:master
Open
Verilator testbench for ISA tests#8
brabect1 wants to merge 4 commits into
SI-RISCV:masterfrom 
brabect1:master
Conversation
@brabect1
@brabect1brabect1
commented
Aug 7, 2018

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This pull requests adds a testbench and Makefile to run ISA tests against RTL with Verilator.
There are minor changes in RTL to make it work with Verilator. Minor changes also made in fpga and SDK Makefiles (these are not needed for the Verilator testbech).
Tomas Brabec-FG6B3Hand others
added 4 commits
July 31, 2018 15:01
Tomas Brabec-FG6B3H
Minor updates in Makefiles.
d0b189c
Changed FPGA build makefile to use e203 as a default CORE and did few minor enhancements.
Updated SDK makefile to let users re-define toolchain binaries names from environment. This shall help using different pre-compiled toolchains.
@brabect1
Added initial support for using Verilator with riscv ISA tests.
0ff7b1a
Testbench and Makefile added into a separate folder (originating from
the existing ISA tests testbench). Minor updates to Verilog code to let
it work with Verilator. Run with v3.924 and --trace enabled (without
--trace the simulation does not converge/end).
@brabect1
Created make targets for running ISA tests in a regression suite.
3da945e
Also added help target to the Makefile so that it becomes the default
one. Added README file with instructions and known limitations. Added
license statements (Apache 2.0).
@brabect1
Fixed instruction for building with older Verilator version.
21e71fb
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, 'i');
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try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '
Verilator testbench for ISA tests by brabect1 · Pull Request #8 · SI-RISCV/e200_opensource · GitHub
Skip to content

This repository was archived by the owner on Mar 24, 2021. It is now read-only.

Verilator testbench for ISA tests - #8
Open
brabect1 wants to merge 4 commits into
SI-RISCV:masterfrom 
brabect1:master
Open
Verilator testbench for ISA tests#8
brabect1 wants to merge 4 commits into
SI-RISCV:masterfrom 
brabect1:master
Conversation
@brabect1
@brabect1brabect1
commented
Aug 7, 2018

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This pull requests adds a testbench and Makefile to run ISA tests against RTL with Verilator.
There are minor changes in RTL to make it work with Verilator. Minor changes also made in fpga and SDK Makefiles (these are not needed for the Verilator testbech).
Tomas Brabec-FG6B3Hand others
added 4 commits
July 31, 2018 15:01
Tomas Brabec-FG6B3H
Minor updates in Makefiles.
d0b189c
Changed FPGA build makefile to use e203 as a default CORE and did few minor enhancements.
Updated SDK makefile to let users re-define toolchain binaries names from environment. This shall help using different pre-compiled toolchains.
@brabect1
Added initial support for using Verilator with riscv ISA tests.
0ff7b1a
Testbench and Makefile added into a separate folder (originating from
the existing ISA tests testbench). Minor updates to Verilog code to let
it work with Verilator. Run with v3.924 and --trace enabled (without
--trace the simulation does not converge/end).
@brabect1
Created make targets for running ISA tests in a regression suite.
3da945e
Also added help target to the Makefile so that it becomes the default
one. Added README file with instructions and known limitations. Added
license statements (Apache 2.0).
@brabect1
Fixed instruction for building with older Verilator version.
21e71fb
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@brabect1

, 'i');
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})();
Verilator testbench for ISA tests by brabect1 · Pull Request #8 · SI-RISCV/e200_opensource · GitHub
Skip to content

This repository was archived by the owner on Mar 24, 2021. It is now read-only.

Verilator testbench for ISA tests - #8
Open
brabect1 wants to merge 4 commits into
SI-RISCV:masterfrom 
brabect1:master
Open
Verilator testbench for ISA tests#8
brabect1 wants to merge 4 commits into
SI-RISCV:masterfrom 
brabect1:master
Conversation
@brabect1
@brabect1brabect1
commented
Aug 7, 2018

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This pull requests adds a testbench and Makefile to run ISA tests against RTL with Verilator.
There are minor changes in RTL to make it work with Verilator. Minor changes also made in fpga and SDK Makefiles (these are not needed for the Verilator testbech).
Tomas Brabec-FG6B3Hand others
added 4 commits
July 31, 2018 15:01
Tomas Brabec-FG6B3H
Minor updates in Makefiles.
d0b189c
Changed FPGA build makefile to use e203 as a default CORE and did few minor enhancements.
Updated SDK makefile to let users re-define toolchain binaries names from environment. This shall help using different pre-compiled toolchains.
@brabect1
Added initial support for using Verilator with riscv ISA tests.
0ff7b1a
Testbench and Makefile added into a separate folder (originating from
the existing ISA tests testbench). Minor updates to Verilog code to let
it work with Verilator. Run with v3.924 and --trace enabled (without
--trace the simulation does not converge/end).
@brabect1
Created make targets for running ISA tests in a regression suite.
3da945e
Also added help target to the Makefile so that it becomes the default
one. Added README file with instructions and known limitations. Added
license statements (Apache 2.0).
@brabect1
Fixed instruction for building with older Verilator version.
21e71fb
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