Verilator testbench for ISA tests

fpga/common.mk

@@ -7,7 +7,7 @@
 # - CONFIG
 # - FPGA_DIR
 
-CORE = e201
+CORE = e203
 PATCHVERILOG ?= ""
 
 
@@ -25,8 +25,7 @@ install:
 	sed -i '1i\`define FPGA_SOURCE\' ${INSTALL_RTL}/core/${CORE}_defines.v
 
 EXTRA_FPGA_VSRCS := 
-verilog := $(wildcard ${INSTALL_RTL}/*/*.v)
-verilog += $(wildcard ${INSTALL_RTL}/*.v)
+verilog =$(wildcard ${INSTALL_RTL}/*/*.v ${INSTALL_RTL}/*.v)
 
 
 # Build .mcs
@@ -42,7 +41,7 @@ bit : install
 
 
 .PHONY: setup
-setup: 
+setup: install
 	BASEDIR=${base_dir} VSRCS="$(verilog)" EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) setup
 
 

rtl/e203/core/e203_clkgate.v

@@ -46,7 +46,7 @@ module e203_clkgate (
 
 `ifndef FPGA_SOURCE//{
 
-reg enb;
+reg enb /*verilator clock_enable*/;
 
 always@(*)
  if (!clk_in)

rtl/e203/general/sirv_sim_ram.v

@@ -48,7 +48,7 @@ module sirv_sim_ram
  output [DW-1:0] dout
 );
 
- reg [DW-1:0] mem_r [0:DP-1];
+ reg [0:DP-1] [DW-1:0] mem_r;
  reg [AW-1:0] addr_r;
  wire [MW-1:0] wen;
  wire ren;

sirv-e-sdk/Makefile

@@ -108,20 +108,28 @@ toolchain_prefix := $(toolchain_builddir)/prefix
 
 RISCV_PATH ?= $(toolchain_prefix)
 
+ifeq ($(GCCVER),)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-ar)
+endif
+
 ifeq ($(GCCVER),6)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
 endif
 
 ifeq ($(GCCVER),7)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
 endif
 
 PATH := $(abspath $(RISCV_PATH)/bin):$(PATH)
@@ -198,6 +206,7 @@ PROGRAM_DIR = software/$(PROGRAM)
 PROGRAM_ELF = software/$(PROGRAM)/$(PROGRAM)
 
 .PHONY: software_clean
+clean: software_clean
 software_clean:
 	$(MAKE) -C $(PROGRAM_DIR) BSP_BASE=$(abspath bsp) BOARD=$(BOARD) clean
 

verilator/Makefile

@@ -0,0 +1,78 @@
+# Copyright 2018 Tomas Brabec
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# 
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+SHELL=bash
+
+vdir = ../rtl/e203
+vsrc = tb_verilator.v $(foreach d,$(wildcard $(vdir)/*),$(wildcard $(d)/*.*v*))
+csrc = sim.cpp
+cflags =
+objdir = obj
+obj = $(csrc:%.cpp=%)
+vflags = $(if $(cflags),-CFLAGS $(cflags)) --cc --exe --Mdir $(objdir) +incdir+$(vdir)/core +incdir+$(vdir)/perips \
+ --top-module tb_verilator \
+ -Wno-WIDTH -Wno-UNOPTFLAT -Wno-CASEINCOMPLETE -Wno-LITENDIAN
+vflags_extra = --trace
+
+isa_test_patts ?= rv32ui* rv32um* rv32uc* rv32ua* rv32mi*
+isa_test_dir ?= ../riscv-tools/riscv-tests/isa/generated
+isa_tests ?= $(basename $(notdir $(wildcard $(foreach p,$(isa_test_patts),$(isa_test_dir)/$(p).verilog))))
+
+
+.PHONY: help
+help:
+	@echo -e "Usage:\n\tmake [ooptions] [target] [<variable>=<value>]"
+	@echo -e "\nTargets:"
+	@echo -e " help prints this help message"
+	@echo -e " list-tests lists available ISA tests"
+	@echo -e " build creates a testbench binary ($(objdir)/$(obj))"
+	@echo -e " regression runs all tests listed by 'list-tests'"
+	@echo -e " test-<name> runs a single test"
+	@echo -e " clean delete all outputs"
+	@echo -e "\nVariables:"
+	@echo -e " isa_test_patts space separated list of patterns of ISA tests"
+	@echo -e " (actual: '$(isa_test_patts)')"
+	@echo -e " isa_tests space separated list of tests to run for 'regression',"
+	@echo -e " use 'make list' to display the corresponding list"
+	@echo -e " cflags extra C++ compiler flags"
+	@echo -e " use cflags='-DVCDTRACE=1' to enable VCD dump into dump.vcd file."
+	@echo -e "\nExamples:"
+	@echo -e " make build test-rv32ui-p-xori"
+	@echo -e " make regression isa_tests=rv32ui-p-xori"
+	@echo -e " make regression isa_patts='rv32ui*'"
+	@echo -e ""
+
+.PHONY: list-tests list
+list list-tests:
+	@echo $(isa_tests)
+
+
+.PHONY: all build
+all build: $(objdir)/$(obj)
+
+$(objdir)/$(obj): $(vsrc) $(csrc)
+	verilator $(vflags) $(vflags_extra) -o $(notdir $(obj)) $(csrc) $(vsrc)
+	make -C $(objdir) -f Vtb_verilator.mk
+
+.PHONY: clean
+clean:
+	rm -rf $(objdir) results dump.vcd && for f in *.verilog; do if [ -L $${f} ]; then unlink $${f}; fi; done
+
+.PHONY: regression
+regression: $(isa_tests:%=test-%)
+
+test-%: $(isa_test_dir)/%.verilog
+	@test -e $*.verilog || ln -s $<
+	@mkdir -p results && echo "Running '$*' test ..." && $(objdir)/$(obj) +TESTCASE=$* > results/$*.log
+

verilator/README.md

@@ -0,0 +1,100 @@
+ISA Tests under Verilator
+=========================
+
+This folder contains a Verilator testbench to exercise RTL against ISA
+[riscv-tests](https://github.com/riscv/riscv-tests).
+
+The testbench was tested with Verilator 3.924 and should work out of the box
+with 3.922 (as the 1st version supporting SV `assert property`). For earlier
+versions one needs to verilate with `+define+DISABLE_SV_ASSERTIONS=1`.
+
+Limitations
+-----------
+
+- Regressions support pre-compiled versions of [riscv-tests](https://github.com/riscv/riscv-tests)
+ available in `riscv-tools/riscv-tests/isa/generated` folder.
+
+- Hard-coded number of clock cycles. The C++ testbench forces the simulation
+ to stop after 1024 cycles. This may be changed in `sim.cpp`.
+
+- The RTL code needs to be verilated with `--trace` option and a VCD trace
+ instance created in the C++ testbench. Otherwise the simulation does not
+ work/converge.
+
+Installing Verilator
+--------------------
+
+### Installing Packaged Version ###
+
+Instructions from https://github.com/ucb-bar/riscv-sodor
+
+- Ubuntu 17.04 and on
+
+ sudo apt install pkg-config verilator
+
+- Ubuntu 16.04 and earlier
+
+ sudo apt install pkg-config
+ wget http://mirrors.kernel.org/ubuntu/pool/universe/v/verilator/verilator_3.900-1_amd64.deb
+ sudo dpkg -i verilator_3.900-1_amd64.deb
+
+### Building from Source ###
+
+Instructions adapted from https://github.com/ucb-bar/riscv-sodor
+
+ # install packages needed for compilation
+ sudo apt-get install make autoconf g++ flex bison libfl-dev
+
+ # optionally install GtkWave
+ sudo apt-get install gtkwave
+
+ # obtain a released version
+ # (alternatively clone a git repo: http://git.veripool.org/git/verilator)
+ wget https://www.veripool.org/ftp/verilator-3.924.tgz
+ tar -xzf verilator-3.924.tgz
+
+ # compile
+ # (when intending to install, consider using ./configure --prefix=<path>)
+ cd verilator*
+ unset VERILATOR_ROOT
+ ./configure && make
+
+ # set environment
+ export VERILATOR_ROOT=$PWD
+ export PATH=$PATH:$VERILATOR_ROOT/bin
+
+Building Testbench
+------------------
+
+To build with default settings:
+
+ make build
+
+To enable VCD dump into `dump.vcd`. Note that the dumping support is compiled
+into the testbench binary and hence you need to rebuild to turn it on and off.
+
+ make build cflags='-DVCDTRACE=1'
+
+To build with Verilator prior to 3.922:
+
+ make build vflags_extra='--trace +define+DISABLE_SV_ASSERTION=1'
+
+Running
+-------
+
+To run the supported regression test suite:
+
+ make regression
+
+To run a full regression test suite (including e.g. floating-point ISA tests):
+
+ make regression isa_test_patts='*'
+
+To run a single test:
+
+ # either run as a regression suite of one test
+ make regression isa_tests=rv32ui-p-xori
+
+ # or run as a single test
+ make test-rv32ui-p-xori
+

verilator/sim.cpp

@@ -0,0 +1,102 @@
+/*
+Copyright 2018 Tomas Brabec
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include "Vtb_verilator.h"
+#include <verilated.h>
+
+#if VM_TRACE
+#include <verilated_vcd_c.h>
+#endif
+
+vluint64_t simtime = 0; // Current simulation time
+ // This is a 64-bit integer to reduce wrap over issues and
+ // allow modulus. You can also use a double, if you wish.
+
+double sc_time_stamp () { // Called by $time in Verilog
+	return simtime; // converts to double, to match
+ // what SystemC does
+}
+
+int main(int argc, char **argv, char **env) {
+	Verilated::commandArgs(argc, argv);
+	Vtb_verilator* top = new Vtb_verilator;
+	int cnt;
+	simtime = 0;
+
+#if VM_TRACE
+	Verilated::traceEverOn(true);
+ VerilatedVcdC* tfp = new VerilatedVcdC;
+#if VCDTRACE
+	top->trace (tfp, 99);
+ tfp->open ("dump.vcd");
+#endif
+#endif
+
+	// reset
+	top->rst_n = 1;
+	top->clk = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 1;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+
+	while (!Verilated::gotFinish() && cnt < (1 << 15)) {
+ top->clk = 1;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ top->clk = 0;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ cnt++;
+	}
+	delete top;
+
+#if VM_TRACE
+#if VCDTRACE
+	tfp->close();
+#endif
+	delete tfp;
+#endif
+
+	if (!Verilated::gotFinish()) {
+ printf("Simulation time out! Forced stop ...\n");
+ return 1;
+	} else {
+#if VM_COVERAGE
+ VerilatedCov::write("coverage.dat");
+#endif // VM_COVERAGE
+ return 0;
+	}
+}

fpga/common.mk

@@ -7,7 +7,7 @@
 # - CONFIG
 # - FPGA_DIR
 
-CORE = e201
+CORE = e203
 PATCHVERILOG ?= ""
 
 
@@ -25,8 +25,7 @@ install:
 	sed -i '1i\`define FPGA_SOURCE\' ${INSTALL_RTL}/core/${CORE}_defines.v
 
 EXTRA_FPGA_VSRCS := 
-verilog := $(wildcard ${INSTALL_RTL}/*/*.v)
-verilog += $(wildcard ${INSTALL_RTL}/*.v)
+verilog =$(wildcard ${INSTALL_RTL}/*/*.v ${INSTALL_RTL}/*.v)
 
 
 # Build .mcs
@@ -42,7 +41,7 @@ bit : install
 
 
 .PHONY: setup
-setup: 
+setup: install
 	BASEDIR=${base_dir} VSRCS="$(verilog)" EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) setup
 
 

rtl/e203/core/e203_clkgate.v

@@ -46,7 +46,7 @@ module e203_clkgate (
 
 `ifndef FPGA_SOURCE//{
 
-reg enb;
+reg enb /*verilator clock_enable*/;
 
 always@(*)
  if (!clk_in)

rtl/e203/general/sirv_sim_ram.v

@@ -48,7 +48,7 @@ module sirv_sim_ram
  output [DW-1:0] dout
 );
 
- reg [DW-1:0] mem_r [0:DP-1];
+ reg [0:DP-1] [DW-1:0] mem_r;
  reg [AW-1:0] addr_r;
  wire [MW-1:0] wen;
  wire ren;

sirv-e-sdk/Makefile

@@ -108,20 +108,28 @@ toolchain_prefix := $(toolchain_builddir)/prefix
 
 RISCV_PATH ?= $(toolchain_prefix)
 
+ifeq ($(GCCVER),)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-ar)
+endif
+
 ifeq ($(GCCVER),6)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
 endif
 
 ifeq ($(GCCVER),7)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
 endif
 
 PATH := $(abspath $(RISCV_PATH)/bin):$(PATH)
@@ -198,6 +206,7 @@ PROGRAM_DIR = software/$(PROGRAM)
 PROGRAM_ELF = software/$(PROGRAM)/$(PROGRAM)
 
 .PHONY: software_clean
+clean: software_clean
 software_clean:
 	$(MAKE) -C $(PROGRAM_DIR) BSP_BASE=$(abspath bsp) BOARD=$(BOARD) clean
 

verilator/Makefile

@@ -0,0 +1,78 @@
+# Copyright 2018 Tomas Brabec
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# 
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+SHELL=bash
+
+vdir = ../rtl/e203
+vsrc = tb_verilator.v $(foreach d,$(wildcard $(vdir)/*),$(wildcard $(d)/*.*v*))
+csrc = sim.cpp
+cflags =
+objdir = obj
+obj = $(csrc:%.cpp=%)
+vflags = $(if $(cflags),-CFLAGS $(cflags)) --cc --exe --Mdir $(objdir) +incdir+$(vdir)/core +incdir+$(vdir)/perips \
+ --top-module tb_verilator \
+ -Wno-WIDTH -Wno-UNOPTFLAT -Wno-CASEINCOMPLETE -Wno-LITENDIAN
+vflags_extra = --trace
+
+isa_test_patts ?= rv32ui* rv32um* rv32uc* rv32ua* rv32mi*
+isa_test_dir ?= ../riscv-tools/riscv-tests/isa/generated
+isa_tests ?= $(basename $(notdir $(wildcard $(foreach p,$(isa_test_patts),$(isa_test_dir)/$(p).verilog))))
+
+
+.PHONY: help
+help:
+	@echo -e "Usage:\n\tmake [ooptions] [target] [<variable>=<value>]"
+	@echo -e "\nTargets:"
+	@echo -e " help prints this help message"
+	@echo -e " list-tests lists available ISA tests"
+	@echo -e " build creates a testbench binary ($(objdir)/$(obj))"
+	@echo -e " regression runs all tests listed by 'list-tests'"
+	@echo -e " test-<name> runs a single test"
+	@echo -e " clean delete all outputs"
+	@echo -e "\nVariables:"
+	@echo -e " isa_test_patts space separated list of patterns of ISA tests"
+	@echo -e " (actual: '$(isa_test_patts)')"
+	@echo -e " isa_tests space separated list of tests to run for 'regression',"
+	@echo -e " use 'make list' to display the corresponding list"
+	@echo -e " cflags extra C++ compiler flags"
+	@echo -e " use cflags='-DVCDTRACE=1' to enable VCD dump into dump.vcd file."
+	@echo -e "\nExamples:"
+	@echo -e " make build test-rv32ui-p-xori"
+	@echo -e " make regression isa_tests=rv32ui-p-xori"
+	@echo -e " make regression isa_patts='rv32ui*'"
+	@echo -e ""
+
+.PHONY: list-tests list
+list list-tests:
+	@echo $(isa_tests)
+
+
+.PHONY: all build
+all build: $(objdir)/$(obj)
+
+$(objdir)/$(obj): $(vsrc) $(csrc)
+	verilator $(vflags) $(vflags_extra) -o $(notdir $(obj)) $(csrc) $(vsrc)
+	make -C $(objdir) -f Vtb_verilator.mk
+
+.PHONY: clean
+clean:
+	rm -rf $(objdir) results dump.vcd && for f in *.verilog; do if [ -L $${f} ]; then unlink $${f}; fi; done
+
+.PHONY: regression
+regression: $(isa_tests:%=test-%)
+
+test-%: $(isa_test_dir)/%.verilog
+	@test -e $*.verilog || ln -s $<
+	@mkdir -p results && echo "Running '$*' test ..." && $(objdir)/$(obj) +TESTCASE=$* > results/$*.log
+

verilator/README.md

@@ -0,0 +1,100 @@
+ISA Tests under Verilator
+=========================
+
+This folder contains a Verilator testbench to exercise RTL against ISA
+[riscv-tests](https://github.com/riscv/riscv-tests).
+
+The testbench was tested with Verilator 3.924 and should work out of the box
+with 3.922 (as the 1st version supporting SV `assert property`). For earlier
+versions one needs to verilate with `+define+DISABLE_SV_ASSERTIONS=1`.
+
+Limitations
+-----------
+
+- Regressions support pre-compiled versions of [riscv-tests](https://github.com/riscv/riscv-tests)
+ available in `riscv-tools/riscv-tests/isa/generated` folder.
+
+- Hard-coded number of clock cycles. The C++ testbench forces the simulation
+ to stop after 1024 cycles. This may be changed in `sim.cpp`.
+
+- The RTL code needs to be verilated with `--trace` option and a VCD trace
+ instance created in the C++ testbench. Otherwise the simulation does not
+ work/converge.
+
+Installing Verilator
+--------------------
+
+### Installing Packaged Version ###
+
+Instructions from https://github.com/ucb-bar/riscv-sodor
+
+- Ubuntu 17.04 and on
+
+ sudo apt install pkg-config verilator
+
+- Ubuntu 16.04 and earlier
+
+ sudo apt install pkg-config
+ wget http://mirrors.kernel.org/ubuntu/pool/universe/v/verilator/verilator_3.900-1_amd64.deb
+ sudo dpkg -i verilator_3.900-1_amd64.deb
+
+### Building from Source ###
+
+Instructions adapted from https://github.com/ucb-bar/riscv-sodor
+
+ # install packages needed for compilation
+ sudo apt-get install make autoconf g++ flex bison libfl-dev
+
+ # optionally install GtkWave
+ sudo apt-get install gtkwave
+
+ # obtain a released version
+ # (alternatively clone a git repo: http://git.veripool.org/git/verilator)
+ wget https://www.veripool.org/ftp/verilator-3.924.tgz
+ tar -xzf verilator-3.924.tgz
+
+ # compile
+ # (when intending to install, consider using ./configure --prefix=<path>)
+ cd verilator*
+ unset VERILATOR_ROOT
+ ./configure && make
+
+ # set environment
+ export VERILATOR_ROOT=$PWD
+ export PATH=$PATH:$VERILATOR_ROOT/bin
+
+Building Testbench
+------------------
+
+To build with default settings:
+
+ make build
+
+To enable VCD dump into `dump.vcd`. Note that the dumping support is compiled
+into the testbench binary and hence you need to rebuild to turn it on and off.
+
+ make build cflags='-DVCDTRACE=1'
+
+To build with Verilator prior to 3.922:
+
+ make build vflags_extra='--trace +define+DISABLE_SV_ASSERTION=1'
+
+Running
+-------
+
+To run the supported regression test suite:
+
+ make regression
+
+To run a full regression test suite (including e.g. floating-point ISA tests):
+
+ make regression isa_test_patts='*'
+
+To run a single test:
+
+ # either run as a regression suite of one test
+ make regression isa_tests=rv32ui-p-xori
+
+ # or run as a single test
+ make test-rv32ui-p-xori
+

verilator/sim.cpp

@@ -0,0 +1,102 @@
+/*
+Copyright 2018 Tomas Brabec
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include "Vtb_verilator.h"
+#include <verilated.h>
+
+#if VM_TRACE
+#include <verilated_vcd_c.h>
+#endif
+
+vluint64_t simtime = 0; // Current simulation time
+ // This is a 64-bit integer to reduce wrap over issues and
+ // allow modulus. You can also use a double, if you wish.
+
+double sc_time_stamp () { // Called by $time in Verilog
+	return simtime; // converts to double, to match
+ // what SystemC does
+}
+
+int main(int argc, char **argv, char **env) {
+	Verilated::commandArgs(argc, argv);
+	Vtb_verilator* top = new Vtb_verilator;
+	int cnt;
+	simtime = 0;
+
+#if VM_TRACE
+	Verilated::traceEverOn(true);
+ VerilatedVcdC* tfp = new VerilatedVcdC;
+#if VCDTRACE
+	top->trace (tfp, 99);
+ tfp->open ("dump.vcd");
+#endif
+#endif
+
+	// reset
+	top->rst_n = 1;
+	top->clk = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 1;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+
+	while (!Verilated::gotFinish() && cnt < (1 << 15)) {
+ top->clk = 1;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ top->clk = 0;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ cnt++;
+	}
+	delete top;
+
+#if VM_TRACE
+#if VCDTRACE
+	tfp->close();
+#endif
+	delete tfp;
+#endif
+
+	if (!Verilated::gotFinish()) {
+ printf("Simulation time out! Forced stop ...\n");
+ return 1;
+	} else {
+#if VM_COVERAGE
+ VerilatedCov::write("coverage.dat");
+#endif // VM_COVERAGE
+ return 0;
+	}
+}

fpga/common.mk

@@ -7,7 +7,7 @@
 # - CONFIG
 # - FPGA_DIR
 
-CORE = e201
+CORE = e203
 PATCHVERILOG ?= ""
 
 
@@ -25,8 +25,7 @@ install:
 	sed -i '1i\`define FPGA_SOURCE\' ${INSTALL_RTL}/core/${CORE}_defines.v
 
 EXTRA_FPGA_VSRCS := 
-verilog := $(wildcard ${INSTALL_RTL}/*/*.v)
-verilog += $(wildcard ${INSTALL_RTL}/*.v)
+verilog =$(wildcard ${INSTALL_RTL}/*/*.v ${INSTALL_RTL}/*.v)
 
 
 # Build .mcs
@@ -42,7 +41,7 @@ bit : install
 
 
 .PHONY: setup
-setup: 
+setup: install
 	BASEDIR=${base_dir} VSRCS="$(verilog)" EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) setup
 
 

rtl/e203/core/e203_clkgate.v

@@ -46,7 +46,7 @@ module e203_clkgate (
 
 `ifndef FPGA_SOURCE//{
 
-reg enb;
+reg enb /*verilator clock_enable*/;
 
 always@(*)
  if (!clk_in)

rtl/e203/general/sirv_sim_ram.v

@@ -48,7 +48,7 @@ module sirv_sim_ram
  output [DW-1:0] dout
 );
 
- reg [DW-1:0] mem_r [0:DP-1];
+ reg [0:DP-1] [DW-1:0] mem_r;
  reg [AW-1:0] addr_r;
  wire [MW-1:0] wen;
  wire ren;

sirv-e-sdk/Makefile

@@ -108,20 +108,28 @@ toolchain_prefix := $(toolchain_builddir)/prefix
 
 RISCV_PATH ?= $(toolchain_prefix)
 
+ifeq ($(GCCVER),)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-ar)
+endif
+
 ifeq ($(GCCVER),6)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
 endif
 
 ifeq ($(GCCVER),7)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
 endif
 
 PATH := $(abspath $(RISCV_PATH)/bin):$(PATH)
@@ -198,6 +206,7 @@ PROGRAM_DIR = software/$(PROGRAM)
 PROGRAM_ELF = software/$(PROGRAM)/$(PROGRAM)
 
 .PHONY: software_clean
+clean: software_clean
 software_clean:
 	$(MAKE) -C $(PROGRAM_DIR) BSP_BASE=$(abspath bsp) BOARD=$(BOARD) clean
 

verilator/Makefile

@@ -0,0 +1,78 @@
+# Copyright 2018 Tomas Brabec
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# 
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+SHELL=bash
+
+vdir = ../rtl/e203
+vsrc = tb_verilator.v $(foreach d,$(wildcard $(vdir)/*),$(wildcard $(d)/*.*v*))
+csrc = sim.cpp
+cflags =
+objdir = obj
+obj = $(csrc:%.cpp=%)
+vflags = $(if $(cflags),-CFLAGS $(cflags)) --cc --exe --Mdir $(objdir) +incdir+$(vdir)/core +incdir+$(vdir)/perips \
+ --top-module tb_verilator \
+ -Wno-WIDTH -Wno-UNOPTFLAT -Wno-CASEINCOMPLETE -Wno-LITENDIAN
+vflags_extra = --trace
+
+isa_test_patts ?= rv32ui* rv32um* rv32uc* rv32ua* rv32mi*
+isa_test_dir ?= ../riscv-tools/riscv-tests/isa/generated
+isa_tests ?= $(basename $(notdir $(wildcard $(foreach p,$(isa_test_patts),$(isa_test_dir)/$(p).verilog))))
+
+
+.PHONY: help
+help:
+	@echo -e "Usage:\n\tmake [ooptions] [target] [<variable>=<value>]"
+	@echo -e "\nTargets:"
+	@echo -e " help prints this help message"
+	@echo -e " list-tests lists available ISA tests"
+	@echo -e " build creates a testbench binary ($(objdir)/$(obj))"
+	@echo -e " regression runs all tests listed by 'list-tests'"
+	@echo -e " test-<name> runs a single test"
+	@echo -e " clean delete all outputs"
+	@echo -e "\nVariables:"
+	@echo -e " isa_test_patts space separated list of patterns of ISA tests"
+	@echo -e " (actual: '$(isa_test_patts)')"
+	@echo -e " isa_tests space separated list of tests to run for 'regression',"
+	@echo -e " use 'make list' to display the corresponding list"
+	@echo -e " cflags extra C++ compiler flags"
+	@echo -e " use cflags='-DVCDTRACE=1' to enable VCD dump into dump.vcd file."
+	@echo -e "\nExamples:"
+	@echo -e " make build test-rv32ui-p-xori"
+	@echo -e " make regression isa_tests=rv32ui-p-xori"
+	@echo -e " make regression isa_patts='rv32ui*'"
+	@echo -e ""
+
+.PHONY: list-tests list
+list list-tests:
+	@echo $(isa_tests)
+
+
+.PHONY: all build
+all build: $(objdir)/$(obj)
+
+$(objdir)/$(obj): $(vsrc) $(csrc)
+	verilator $(vflags) $(vflags_extra) -o $(notdir $(obj)) $(csrc) $(vsrc)
+	make -C $(objdir) -f Vtb_verilator.mk
+
+.PHONY: clean
+clean:
+	rm -rf $(objdir) results dump.vcd && for f in *.verilog; do if [ -L $${f} ]; then unlink $${f}; fi; done
+
+.PHONY: regression
+regression: $(isa_tests:%=test-%)
+
+test-%: $(isa_test_dir)/%.verilog
+	@test -e $*.verilog || ln -s $<
+	@mkdir -p results && echo "Running '$*' test ..." && $(objdir)/$(obj) +TESTCASE=$* > results/$*.log
+

verilator/README.md

@@ -0,0 +1,100 @@
+ISA Tests under Verilator
+=========================
+
+This folder contains a Verilator testbench to exercise RTL against ISA
+[riscv-tests](https://github.com/riscv/riscv-tests).
+
+The testbench was tested with Verilator 3.924 and should work out of the box
+with 3.922 (as the 1st version supporting SV `assert property`). For earlier
+versions one needs to verilate with `+define+DISABLE_SV_ASSERTIONS=1`.
+
+Limitations
+-----------
+
+- Regressions support pre-compiled versions of [riscv-tests](https://github.com/riscv/riscv-tests)
+ available in `riscv-tools/riscv-tests/isa/generated` folder.
+
+- Hard-coded number of clock cycles. The C++ testbench forces the simulation
+ to stop after 1024 cycles. This may be changed in `sim.cpp`.
+
+- The RTL code needs to be verilated with `--trace` option and a VCD trace
+ instance created in the C++ testbench. Otherwise the simulation does not
+ work/converge.
+
+Installing Verilator
+--------------------
+
+### Installing Packaged Version ###
+
+Instructions from https://github.com/ucb-bar/riscv-sodor
+
+- Ubuntu 17.04 and on
+
+ sudo apt install pkg-config verilator
+
+- Ubuntu 16.04 and earlier
+
+ sudo apt install pkg-config
+ wget http://mirrors.kernel.org/ubuntu/pool/universe/v/verilator/verilator_3.900-1_amd64.deb
+ sudo dpkg -i verilator_3.900-1_amd64.deb
+
+### Building from Source ###
+
+Instructions adapted from https://github.com/ucb-bar/riscv-sodor
+
+ # install packages needed for compilation
+ sudo apt-get install make autoconf g++ flex bison libfl-dev
+
+ # optionally install GtkWave
+ sudo apt-get install gtkwave
+
+ # obtain a released version
+ # (alternatively clone a git repo: http://git.veripool.org/git/verilator)
+ wget https://www.veripool.org/ftp/verilator-3.924.tgz
+ tar -xzf verilator-3.924.tgz
+
+ # compile
+ # (when intending to install, consider using ./configure --prefix=<path>)
+ cd verilator*
+ unset VERILATOR_ROOT
+ ./configure && make
+
+ # set environment
+ export VERILATOR_ROOT=$PWD
+ export PATH=$PATH:$VERILATOR_ROOT/bin
+
+Building Testbench
+------------------
+
+To build with default settings:
+
+ make build
+
+To enable VCD dump into `dump.vcd`. Note that the dumping support is compiled
+into the testbench binary and hence you need to rebuild to turn it on and off.
+
+ make build cflags='-DVCDTRACE=1'
+
+To build with Verilator prior to 3.922:
+
+ make build vflags_extra='--trace +define+DISABLE_SV_ASSERTION=1'
+
+Running
+-------
+
+To run the supported regression test suite:
+
+ make regression
+
+To run a full regression test suite (including e.g. floating-point ISA tests):
+
+ make regression isa_test_patts='*'
+
+To run a single test:
+
+ # either run as a regression suite of one test
+ make regression isa_tests=rv32ui-p-xori
+
+ # or run as a single test
+ make test-rv32ui-p-xori
+

verilator/sim.cpp

@@ -0,0 +1,102 @@
+/*
+Copyright 2018 Tomas Brabec
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include "Vtb_verilator.h"
+#include <verilated.h>
+
+#if VM_TRACE
+#include <verilated_vcd_c.h>
+#endif
+
+vluint64_t simtime = 0; // Current simulation time
+ // This is a 64-bit integer to reduce wrap over issues and
+ // allow modulus. You can also use a double, if you wish.
+
+double sc_time_stamp () { // Called by $time in Verilog
+	return simtime; // converts to double, to match
+ // what SystemC does
+}
+
+int main(int argc, char **argv, char **env) {
+	Verilated::commandArgs(argc, argv);
+	Vtb_verilator* top = new Vtb_verilator;
+	int cnt;
+	simtime = 0;
+
+#if VM_TRACE
+	Verilated::traceEverOn(true);
+ VerilatedVcdC* tfp = new VerilatedVcdC;
+#if VCDTRACE
+	top->trace (tfp, 99);
+ tfp->open ("dump.vcd");
+#endif
+#endif
+
+	// reset
+	top->rst_n = 1;
+	top->clk = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 1;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+
+	while (!Verilated::gotFinish() && cnt < (1 << 15)) {
+ top->clk = 1;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ top->clk = 0;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ cnt++;
+	}
+	delete top;
+
+#if VM_TRACE
+#if VCDTRACE
+	tfp->close();
+#endif
+	delete tfp;
+#endif
+
+	if (!Verilated::gotFinish()) {
+ printf("Simulation time out! Forced stop ...\n");
+ return 1;
+	} else {
+#if VM_COVERAGE
+ VerilatedCov::write("coverage.dat");
+#endif // VM_COVERAGE
+ return 0;
+	}
+}

fpga/common.mk

@@ -7,7 +7,7 @@
 # - CONFIG
 # - FPGA_DIR
 
-CORE = e201
+CORE = e203
 PATCHVERILOG ?= ""
 
 
@@ -25,8 +25,7 @@ install:
 	sed -i '1i\`define FPGA_SOURCE\' ${INSTALL_RTL}/core/${CORE}_defines.v
 
 EXTRA_FPGA_VSRCS := 
-verilog := $(wildcard ${INSTALL_RTL}/*/*.v)
-verilog += $(wildcard ${INSTALL_RTL}/*.v)
+verilog =$(wildcard ${INSTALL_RTL}/*/*.v ${INSTALL_RTL}/*.v)
 
 
 # Build .mcs
@@ -42,7 +41,7 @@ bit : install
 
 
 .PHONY: setup
-setup: 
+setup: install
 	BASEDIR=${base_dir} VSRCS="$(verilog)" EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) setup
 
 

rtl/e203/core/e203_clkgate.v

@@ -46,7 +46,7 @@ module e203_clkgate (
 
 `ifndef FPGA_SOURCE//{
 
-reg enb;
+reg enb /*verilator clock_enable*/;
 
 always@(*)
  if (!clk_in)

rtl/e203/general/sirv_sim_ram.v

@@ -48,7 +48,7 @@ module sirv_sim_ram
  output [DW-1:0] dout
 );
 
- reg [DW-1:0] mem_r [0:DP-1];
+ reg [0:DP-1] [DW-1:0] mem_r;
  reg [AW-1:0] addr_r;
  wire [MW-1:0] wen;
  wire ren;

sirv-e-sdk/Makefile

@@ -108,20 +108,28 @@ toolchain_prefix := $(toolchain_builddir)/prefix
 
 RISCV_PATH ?= $(toolchain_prefix)
 
+ifeq ($(GCCVER),)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-ar)
+endif
+
 ifeq ($(GCCVER),6)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
 endif
 
 ifeq ($(GCCVER),7)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
 endif
 
 PATH := $(abspath $(RISCV_PATH)/bin):$(PATH)
@@ -198,6 +206,7 @@ PROGRAM_DIR = software/$(PROGRAM)
 PROGRAM_ELF = software/$(PROGRAM)/$(PROGRAM)
 
 .PHONY: software_clean
+clean: software_clean
 software_clean:
 	$(MAKE) -C $(PROGRAM_DIR) BSP_BASE=$(abspath bsp) BOARD=$(BOARD) clean
 

verilator/Makefile

@@ -0,0 +1,78 @@
+# Copyright 2018 Tomas Brabec
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# 
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+SHELL=bash
+
+vdir = ../rtl/e203
+vsrc = tb_verilator.v $(foreach d,$(wildcard $(vdir)/*),$(wildcard $(d)/*.*v*))
+csrc = sim.cpp
+cflags =
+objdir = obj
+obj = $(csrc:%.cpp=%)
+vflags = $(if $(cflags),-CFLAGS $(cflags)) --cc --exe --Mdir $(objdir) +incdir+$(vdir)/core +incdir+$(vdir)/perips \
+ --top-module tb_verilator \
+ -Wno-WIDTH -Wno-UNOPTFLAT -Wno-CASEINCOMPLETE -Wno-LITENDIAN
+vflags_extra = --trace
+
+isa_test_patts ?= rv32ui* rv32um* rv32uc* rv32ua* rv32mi*
+isa_test_dir ?= ../riscv-tools/riscv-tests/isa/generated
+isa_tests ?= $(basename $(notdir $(wildcard $(foreach p,$(isa_test_patts),$(isa_test_dir)/$(p).verilog))))
+
+
+.PHONY: help
+help:
+	@echo -e "Usage:\n\tmake [ooptions] [target] [<variable>=<value>]"
+	@echo -e "\nTargets:"
+	@echo -e " help prints this help message"
+	@echo -e " list-tests lists available ISA tests"
+	@echo -e " build creates a testbench binary ($(objdir)/$(obj))"
+	@echo -e " regression runs all tests listed by 'list-tests'"
+	@echo -e " test-<name> runs a single test"
+	@echo -e " clean delete all outputs"
+	@echo -e "\nVariables:"
+	@echo -e " isa_test_patts space separated list of patterns of ISA tests"
+	@echo -e " (actual: '$(isa_test_patts)')"
+	@echo -e " isa_tests space separated list of tests to run for 'regression',"
+	@echo -e " use 'make list' to display the corresponding list"
+	@echo -e " cflags extra C++ compiler flags"
+	@echo -e " use cflags='-DVCDTRACE=1' to enable VCD dump into dump.vcd file."
+	@echo -e "\nExamples:"
+	@echo -e " make build test-rv32ui-p-xori"
+	@echo -e " make regression isa_tests=rv32ui-p-xori"
+	@echo -e " make regression isa_patts='rv32ui*'"
+	@echo -e ""
+
+.PHONY: list-tests list
+list list-tests:
+	@echo $(isa_tests)
+
+
+.PHONY: all build
+all build: $(objdir)/$(obj)
+
+$(objdir)/$(obj): $(vsrc) $(csrc)
+	verilator $(vflags) $(vflags_extra) -o $(notdir $(obj)) $(csrc) $(vsrc)
+	make -C $(objdir) -f Vtb_verilator.mk
+
+.PHONY: clean
+clean:
+	rm -rf $(objdir) results dump.vcd && for f in *.verilog; do if [ -L $${f} ]; then unlink $${f}; fi; done
+
+.PHONY: regression
+regression: $(isa_tests:%=test-%)
+
+test-%: $(isa_test_dir)/%.verilog
+	@test -e $*.verilog || ln -s $<
+	@mkdir -p results && echo "Running '$*' test ..." && $(objdir)/$(obj) +TESTCASE=$* > results/$*.log
+

verilator/README.md

@@ -0,0 +1,100 @@
+ISA Tests under Verilator
+=========================
+
+This folder contains a Verilator testbench to exercise RTL against ISA
+[riscv-tests](https://github.com/riscv/riscv-tests).
+
+The testbench was tested with Verilator 3.924 and should work out of the box
+with 3.922 (as the 1st version supporting SV `assert property`). For earlier
+versions one needs to verilate with `+define+DISABLE_SV_ASSERTIONS=1`.
+
+Limitations
+-----------
+
+- Regressions support pre-compiled versions of [riscv-tests](https://github.com/riscv/riscv-tests)
+ available in `riscv-tools/riscv-tests/isa/generated` folder.
+
+- Hard-coded number of clock cycles. The C++ testbench forces the simulation
+ to stop after 1024 cycles. This may be changed in `sim.cpp`.
+
+- The RTL code needs to be verilated with `--trace` option and a VCD trace
+ instance created in the C++ testbench. Otherwise the simulation does not
+ work/converge.
+
+Installing Verilator
+--------------------
+
+### Installing Packaged Version ###
+
+Instructions from https://github.com/ucb-bar/riscv-sodor
+
+- Ubuntu 17.04 and on
+
+ sudo apt install pkg-config verilator
+
+- Ubuntu 16.04 and earlier
+
+ sudo apt install pkg-config
+ wget http://mirrors.kernel.org/ubuntu/pool/universe/v/verilator/verilator_3.900-1_amd64.deb
+ sudo dpkg -i verilator_3.900-1_amd64.deb
+
+### Building from Source ###
+
+Instructions adapted from https://github.com/ucb-bar/riscv-sodor
+
+ # install packages needed for compilation
+ sudo apt-get install make autoconf g++ flex bison libfl-dev
+
+ # optionally install GtkWave
+ sudo apt-get install gtkwave
+
+ # obtain a released version
+ # (alternatively clone a git repo: http://git.veripool.org/git/verilator)
+ wget https://www.veripool.org/ftp/verilator-3.924.tgz
+ tar -xzf verilator-3.924.tgz
+
+ # compile
+ # (when intending to install, consider using ./configure --prefix=<path>)
+ cd verilator*
+ unset VERILATOR_ROOT
+ ./configure && make
+
+ # set environment
+ export VERILATOR_ROOT=$PWD
+ export PATH=$PATH:$VERILATOR_ROOT/bin
+
+Building Testbench
+------------------
+
+To build with default settings:
+
+ make build
+
+To enable VCD dump into `dump.vcd`. Note that the dumping support is compiled
+into the testbench binary and hence you need to rebuild to turn it on and off.
+
+ make build cflags='-DVCDTRACE=1'
+
+To build with Verilator prior to 3.922:
+
+ make build vflags_extra='--trace +define+DISABLE_SV_ASSERTION=1'
+
+Running
+-------
+
+To run the supported regression test suite:
+
+ make regression
+
+To run a full regression test suite (including e.g. floating-point ISA tests):
+
+ make regression isa_test_patts='*'
+
+To run a single test:
+
+ # either run as a regression suite of one test
+ make regression isa_tests=rv32ui-p-xori
+
+ # or run as a single test
+ make test-rv32ui-p-xori
+

verilator/sim.cpp

@@ -0,0 +1,102 @@
+/*
+Copyright 2018 Tomas Brabec
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include "Vtb_verilator.h"
+#include <verilated.h>
+
+#if VM_TRACE
+#include <verilated_vcd_c.h>
+#endif
+
+vluint64_t simtime = 0; // Current simulation time
+ // This is a 64-bit integer to reduce wrap over issues and
+ // allow modulus. You can also use a double, if you wish.
+
+double sc_time_stamp () { // Called by $time in Verilog
+	return simtime; // converts to double, to match
+ // what SystemC does
+}
+
+int main(int argc, char **argv, char **env) {
+	Verilated::commandArgs(argc, argv);
+	Vtb_verilator* top = new Vtb_verilator;
+	int cnt;
+	simtime = 0;
+
+#if VM_TRACE
+	Verilated::traceEverOn(true);
+ VerilatedVcdC* tfp = new VerilatedVcdC;
+#if VCDTRACE
+	top->trace (tfp, 99);
+ tfp->open ("dump.vcd");
+#endif
+#endif
+
+	// reset
+	top->rst_n = 1;
+	top->clk = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 1;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+
+	while (!Verilated::gotFinish() && cnt < (1 << 15)) {
+ top->clk = 1;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ top->clk = 0;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ cnt++;
+	}
+	delete top;
+
+#if VM_TRACE
+#if VCDTRACE
+	tfp->close();
+#endif
+	delete tfp;
+#endif
+
+	if (!Verilated::gotFinish()) {
+ printf("Simulation time out! Forced stop ...\n");
+ return 1;
+	} else {
+#if VM_COVERAGE
+ VerilatedCov::write("coverage.dat");
+#endif // VM_COVERAGE
+ return 0;
+	}
+}

fpga/common.mk

@@ -7,7 +7,7 @@
 # - CONFIG
 # - FPGA_DIR
 
-CORE = e201
+CORE = e203
 PATCHVERILOG ?= ""
 
 
@@ -25,8 +25,7 @@ install:
 	sed -i '1i\`define FPGA_SOURCE\' ${INSTALL_RTL}/core/${CORE}_defines.v
 
 EXTRA_FPGA_VSRCS := 
-verilog := $(wildcard ${INSTALL_RTL}/*/*.v)
-verilog += $(wildcard ${INSTALL_RTL}/*.v)
+verilog =$(wildcard ${INSTALL_RTL}/*/*.v ${INSTALL_RTL}/*.v)
 
 
 # Build .mcs
@@ -42,7 +41,7 @@ bit : install
 
 
 .PHONY: setup
-setup: 
+setup: install
 	BASEDIR=${base_dir} VSRCS="$(verilog)" EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) setup
 
 

rtl/e203/core/e203_clkgate.v

@@ -46,7 +46,7 @@ module e203_clkgate (
 
 `ifndef FPGA_SOURCE//{
 
-reg enb;
+reg enb /*verilator clock_enable*/;
 
 always@(*)
  if (!clk_in)

rtl/e203/general/sirv_sim_ram.v

@@ -48,7 +48,7 @@ module sirv_sim_ram
  output [DW-1:0] dout
 );
 
- reg [DW-1:0] mem_r [0:DP-1];
+ reg [0:DP-1] [DW-1:0] mem_r;
  reg [AW-1:0] addr_r;
  wire [MW-1:0] wen;
  wire ren;

sirv-e-sdk/Makefile

@@ -108,20 +108,28 @@ toolchain_prefix := $(toolchain_builddir)/prefix
 
 RISCV_PATH ?= $(toolchain_prefix)
 
+ifeq ($(GCCVER),)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-ar)
+endif
+
 ifeq ($(GCCVER),6)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
 endif
 
 ifeq ($(GCCVER),7)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
 endif
 
 PATH := $(abspath $(RISCV_PATH)/bin):$(PATH)
@@ -198,6 +206,7 @@ PROGRAM_DIR = software/$(PROGRAM)
 PROGRAM_ELF = software/$(PROGRAM)/$(PROGRAM)
 
 .PHONY: software_clean
+clean: software_clean
 software_clean:
 	$(MAKE) -C $(PROGRAM_DIR) BSP_BASE=$(abspath bsp) BOARD=$(BOARD) clean
 

verilator/Makefile

@@ -0,0 +1,78 @@
+# Copyright 2018 Tomas Brabec
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# 
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+SHELL=bash
+
+vdir = ../rtl/e203
+vsrc = tb_verilator.v $(foreach d,$(wildcard $(vdir)/*),$(wildcard $(d)/*.*v*))
+csrc = sim.cpp
+cflags =
+objdir = obj
+obj = $(csrc:%.cpp=%)
+vflags = $(if $(cflags),-CFLAGS $(cflags)) --cc --exe --Mdir $(objdir) +incdir+$(vdir)/core +incdir+$(vdir)/perips \
+ --top-module tb_verilator \
+ -Wno-WIDTH -Wno-UNOPTFLAT -Wno-CASEINCOMPLETE -Wno-LITENDIAN
+vflags_extra = --trace
+
+isa_test_patts ?= rv32ui* rv32um* rv32uc* rv32ua* rv32mi*
+isa_test_dir ?= ../riscv-tools/riscv-tests/isa/generated
+isa_tests ?= $(basename $(notdir $(wildcard $(foreach p,$(isa_test_patts),$(isa_test_dir)/$(p).verilog))))
+
+
+.PHONY: help
+help:
+	@echo -e "Usage:\n\tmake [ooptions] [target] [<variable>=<value>]"
+	@echo -e "\nTargets:"
+	@echo -e " help prints this help message"
+	@echo -e " list-tests lists available ISA tests"
+	@echo -e " build creates a testbench binary ($(objdir)/$(obj))"
+	@echo -e " regression runs all tests listed by 'list-tests'"
+	@echo -e " test-<name> runs a single test"
+	@echo -e " clean delete all outputs"
+	@echo -e "\nVariables:"
+	@echo -e " isa_test_patts space separated list of patterns of ISA tests"
+	@echo -e " (actual: '$(isa_test_patts)')"
+	@echo -e " isa_tests space separated list of tests to run for 'regression',"
+	@echo -e " use 'make list' to display the corresponding list"
+	@echo -e " cflags extra C++ compiler flags"
+	@echo -e " use cflags='-DVCDTRACE=1' to enable VCD dump into dump.vcd file."
+	@echo -e "\nExamples:"
+	@echo -e " make build test-rv32ui-p-xori"
+	@echo -e " make regression isa_tests=rv32ui-p-xori"
+	@echo -e " make regression isa_patts='rv32ui*'"
+	@echo -e ""
+
+.PHONY: list-tests list
+list list-tests:
+	@echo $(isa_tests)
+
+
+.PHONY: all build
+all build: $(objdir)/$(obj)
+
+$(objdir)/$(obj): $(vsrc) $(csrc)
+	verilator $(vflags) $(vflags_extra) -o $(notdir $(obj)) $(csrc) $(vsrc)
+	make -C $(objdir) -f Vtb_verilator.mk
+
+.PHONY: clean
+clean:
+	rm -rf $(objdir) results dump.vcd && for f in *.verilog; do if [ -L $${f} ]; then unlink $${f}; fi; done
+
+.PHONY: regression
+regression: $(isa_tests:%=test-%)
+
+test-%: $(isa_test_dir)/%.verilog
+	@test -e $*.verilog || ln -s $<
+	@mkdir -p results && echo "Running '$*' test ..." && $(objdir)/$(obj) +TESTCASE=$* > results/$*.log
+

verilator/README.md

@@ -0,0 +1,100 @@
+ISA Tests under Verilator
+=========================
+
+This folder contains a Verilator testbench to exercise RTL against ISA
+[riscv-tests](https://github.com/riscv/riscv-tests).
+
+The testbench was tested with Verilator 3.924 and should work out of the box
+with 3.922 (as the 1st version supporting SV `assert property`). For earlier
+versions one needs to verilate with `+define+DISABLE_SV_ASSERTIONS=1`.
+
+Limitations
+-----------
+
+- Regressions support pre-compiled versions of [riscv-tests](https://github.com/riscv/riscv-tests)
+ available in `riscv-tools/riscv-tests/isa/generated` folder.
+
+- Hard-coded number of clock cycles. The C++ testbench forces the simulation
+ to stop after 1024 cycles. This may be changed in `sim.cpp`.
+
+- The RTL code needs to be verilated with `--trace` option and a VCD trace
+ instance created in the C++ testbench. Otherwise the simulation does not
+ work/converge.
+
+Installing Verilator
+--------------------
+
+### Installing Packaged Version ###
+
+Instructions from https://github.com/ucb-bar/riscv-sodor
+
+- Ubuntu 17.04 and on
+
+ sudo apt install pkg-config verilator
+
+- Ubuntu 16.04 and earlier
+
+ sudo apt install pkg-config
+ wget http://mirrors.kernel.org/ubuntu/pool/universe/v/verilator/verilator_3.900-1_amd64.deb
+ sudo dpkg -i verilator_3.900-1_amd64.deb
+
+### Building from Source ###
+
+Instructions adapted from https://github.com/ucb-bar/riscv-sodor
+
+ # install packages needed for compilation
+ sudo apt-get install make autoconf g++ flex bison libfl-dev
+
+ # optionally install GtkWave
+ sudo apt-get install gtkwave
+
+ # obtain a released version
+ # (alternatively clone a git repo: http://git.veripool.org/git/verilator)
+ wget https://www.veripool.org/ftp/verilator-3.924.tgz
+ tar -xzf verilator-3.924.tgz
+
+ # compile
+ # (when intending to install, consider using ./configure --prefix=<path>)
+ cd verilator*
+ unset VERILATOR_ROOT
+ ./configure && make
+
+ # set environment
+ export VERILATOR_ROOT=$PWD
+ export PATH=$PATH:$VERILATOR_ROOT/bin
+
+Building Testbench
+------------------
+
+To build with default settings:
+
+ make build
+
+To enable VCD dump into `dump.vcd`. Note that the dumping support is compiled
+into the testbench binary and hence you need to rebuild to turn it on and off.
+
+ make build cflags='-DVCDTRACE=1'
+
+To build with Verilator prior to 3.922:
+
+ make build vflags_extra='--trace +define+DISABLE_SV_ASSERTION=1'
+
+Running
+-------
+
+To run the supported regression test suite:
+
+ make regression
+
+To run a full regression test suite (including e.g. floating-point ISA tests):
+
+ make regression isa_test_patts='*'
+
+To run a single test:
+
+ # either run as a regression suite of one test
+ make regression isa_tests=rv32ui-p-xori
+
+ # or run as a single test
+ make test-rv32ui-p-xori
+

verilator/sim.cpp

@@ -0,0 +1,102 @@
+/*
+Copyright 2018 Tomas Brabec
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include "Vtb_verilator.h"
+#include <verilated.h>
+
+#if VM_TRACE
+#include <verilated_vcd_c.h>
+#endif
+
+vluint64_t simtime = 0; // Current simulation time
+ // This is a 64-bit integer to reduce wrap over issues and
+ // allow modulus. You can also use a double, if you wish.
+
+double sc_time_stamp () { // Called by $time in Verilog
+	return simtime; // converts to double, to match
+ // what SystemC does
+}
+
+int main(int argc, char **argv, char **env) {
+	Verilated::commandArgs(argc, argv);
+	Vtb_verilator* top = new Vtb_verilator;
+	int cnt;
+	simtime = 0;
+
+#if VM_TRACE
+	Verilated::traceEverOn(true);
+ VerilatedVcdC* tfp = new VerilatedVcdC;
+#if VCDTRACE
+	top->trace (tfp, 99);
+ tfp->open ("dump.vcd");
+#endif
+#endif
+
+	// reset
+	top->rst_n = 1;
+	top->clk = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 1;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+
+	while (!Verilated::gotFinish() && cnt < (1 << 15)) {
+ top->clk = 1;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ top->clk = 0;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ cnt++;
+	}
+	delete top;
+
+#if VM_TRACE
+#if VCDTRACE
+	tfp->close();
+#endif
+	delete tfp;
+#endif
+
+	if (!Verilated::gotFinish()) {
+ printf("Simulation time out! Forced stop ...\n");
+ return 1;
+	} else {
+#if VM_COVERAGE
+ VerilatedCov::write("coverage.dat");
+#endif // VM_COVERAGE
+ return 0;
+	}
+}

fpga/common.mk

@@ -7,7 +7,7 @@
 # - CONFIG
 # - FPGA_DIR
 
-CORE = e201
+CORE = e203
 PATCHVERILOG ?= ""
 
 
@@ -25,8 +25,7 @@ install:
 	sed -i '1i\`define FPGA_SOURCE\' ${INSTALL_RTL}/core/${CORE}_defines.v
 
 EXTRA_FPGA_VSRCS := 
-verilog := $(wildcard ${INSTALL_RTL}/*/*.v)
-verilog += $(wildcard ${INSTALL_RTL}/*.v)
+verilog =$(wildcard ${INSTALL_RTL}/*/*.v ${INSTALL_RTL}/*.v)
 
 
 # Build .mcs
@@ -42,7 +41,7 @@ bit : install
 
 
 .PHONY: setup
-setup: 
+setup: install
 	BASEDIR=${base_dir} VSRCS="$(verilog)" EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) setup
 
 

rtl/e203/core/e203_clkgate.v

@@ -46,7 +46,7 @@ module e203_clkgate (
 
 `ifndef FPGA_SOURCE//{
 
-reg enb;
+reg enb /*verilator clock_enable*/;
 
 always@(*)
  if (!clk_in)

rtl/e203/general/sirv_sim_ram.v

@@ -48,7 +48,7 @@ module sirv_sim_ram
  output [DW-1:0] dout
 );
 
- reg [DW-1:0] mem_r [0:DP-1];
+ reg [0:DP-1] [DW-1:0] mem_r;
  reg [AW-1:0] addr_r;
  wire [MW-1:0] wen;
  wire ren;

sirv-e-sdk/Makefile

@@ -108,20 +108,28 @@ toolchain_prefix := $(toolchain_builddir)/prefix
 
 RISCV_PATH ?= $(toolchain_prefix)
 
+ifeq ($(GCCVER),)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-ar)
+endif
+
 ifeq ($(GCCVER),6)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
 endif
 
 ifeq ($(GCCVER),7)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
 endif
 
 PATH := $(abspath $(RISCV_PATH)/bin):$(PATH)
@@ -198,6 +206,7 @@ PROGRAM_DIR = software/$(PROGRAM)
 PROGRAM_ELF = software/$(PROGRAM)/$(PROGRAM)
 
 .PHONY: software_clean
+clean: software_clean
 software_clean:
 	$(MAKE) -C $(PROGRAM_DIR) BSP_BASE=$(abspath bsp) BOARD=$(BOARD) clean
 

verilator/Makefile

@@ -0,0 +1,78 @@
+# Copyright 2018 Tomas Brabec
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# 
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+SHELL=bash
+
+vdir = ../rtl/e203
+vsrc = tb_verilator.v $(foreach d,$(wildcard $(vdir)/*),$(wildcard $(d)/*.*v*))
+csrc = sim.cpp
+cflags =
+objdir = obj
+obj = $(csrc:%.cpp=%)
+vflags = $(if $(cflags),-CFLAGS $(cflags)) --cc --exe --Mdir $(objdir) +incdir+$(vdir)/core +incdir+$(vdir)/perips \
+ --top-module tb_verilator \
+ -Wno-WIDTH -Wno-UNOPTFLAT -Wno-CASEINCOMPLETE -Wno-LITENDIAN
+vflags_extra = --trace
+
+isa_test_patts ?= rv32ui* rv32um* rv32uc* rv32ua* rv32mi*
+isa_test_dir ?= ../riscv-tools/riscv-tests/isa/generated
+isa_tests ?= $(basename $(notdir $(wildcard $(foreach p,$(isa_test_patts),$(isa_test_dir)/$(p).verilog))))
+
+
+.PHONY: help
+help:
+	@echo -e "Usage:\n\tmake [ooptions] [target] [<variable>=<value>]"
+	@echo -e "\nTargets:"
+	@echo -e " help prints this help message"
+	@echo -e " list-tests lists available ISA tests"
+	@echo -e " build creates a testbench binary ($(objdir)/$(obj))"
+	@echo -e " regression runs all tests listed by 'list-tests'"
+	@echo -e " test-<name> runs a single test"
+	@echo -e " clean delete all outputs"
+	@echo -e "\nVariables:"
+	@echo -e " isa_test_patts space separated list of patterns of ISA tests"
+	@echo -e " (actual: '$(isa_test_patts)')"
+	@echo -e " isa_tests space separated list of tests to run for 'regression',"
+	@echo -e " use 'make list' to display the corresponding list"
+	@echo -e " cflags extra C++ compiler flags"
+	@echo -e " use cflags='-DVCDTRACE=1' to enable VCD dump into dump.vcd file."
+	@echo -e "\nExamples:"
+	@echo -e " make build test-rv32ui-p-xori"
+	@echo -e " make regression isa_tests=rv32ui-p-xori"
+	@echo -e " make regression isa_patts='rv32ui*'"
+	@echo -e ""
+
+.PHONY: list-tests list
+list list-tests:
+	@echo $(isa_tests)
+
+
+.PHONY: all build
+all build: $(objdir)/$(obj)
+
+$(objdir)/$(obj): $(vsrc) $(csrc)
+	verilator $(vflags) $(vflags_extra) -o $(notdir $(obj)) $(csrc) $(vsrc)
+	make -C $(objdir) -f Vtb_verilator.mk
+
+.PHONY: clean
+clean:
+	rm -rf $(objdir) results dump.vcd && for f in *.verilog; do if [ -L $${f} ]; then unlink $${f}; fi; done
+
+.PHONY: regression
+regression: $(isa_tests:%=test-%)
+
+test-%: $(isa_test_dir)/%.verilog
+	@test -e $*.verilog || ln -s $<
+	@mkdir -p results && echo "Running '$*' test ..." && $(objdir)/$(obj) +TESTCASE=$* > results/$*.log
+

verilator/README.md

@@ -0,0 +1,100 @@
+ISA Tests under Verilator
+=========================
+
+This folder contains a Verilator testbench to exercise RTL against ISA
+[riscv-tests](https://github.com/riscv/riscv-tests).
+
+The testbench was tested with Verilator 3.924 and should work out of the box
+with 3.922 (as the 1st version supporting SV `assert property`). For earlier
+versions one needs to verilate with `+define+DISABLE_SV_ASSERTIONS=1`.
+
+Limitations
+-----------
+
+- Regressions support pre-compiled versions of [riscv-tests](https://github.com/riscv/riscv-tests)
+ available in `riscv-tools/riscv-tests/isa/generated` folder.
+
+- Hard-coded number of clock cycles. The C++ testbench forces the simulation
+ to stop after 1024 cycles. This may be changed in `sim.cpp`.
+
+- The RTL code needs to be verilated with `--trace` option and a VCD trace
+ instance created in the C++ testbench. Otherwise the simulation does not
+ work/converge.
+
+Installing Verilator
+--------------------
+
+### Installing Packaged Version ###
+
+Instructions from https://github.com/ucb-bar/riscv-sodor
+
+- Ubuntu 17.04 and on
+
+ sudo apt install pkg-config verilator
+
+- Ubuntu 16.04 and earlier
+
+ sudo apt install pkg-config
+ wget http://mirrors.kernel.org/ubuntu/pool/universe/v/verilator/verilator_3.900-1_amd64.deb
+ sudo dpkg -i verilator_3.900-1_amd64.deb
+
+### Building from Source ###
+
+Instructions adapted from https://github.com/ucb-bar/riscv-sodor
+
+ # install packages needed for compilation
+ sudo apt-get install make autoconf g++ flex bison libfl-dev
+
+ # optionally install GtkWave
+ sudo apt-get install gtkwave
+
+ # obtain a released version
+ # (alternatively clone a git repo: http://git.veripool.org/git/verilator)
+ wget https://www.veripool.org/ftp/verilator-3.924.tgz
+ tar -xzf verilator-3.924.tgz
+
+ # compile
+ # (when intending to install, consider using ./configure --prefix=<path>)
+ cd verilator*
+ unset VERILATOR_ROOT
+ ./configure && make
+
+ # set environment
+ export VERILATOR_ROOT=$PWD
+ export PATH=$PATH:$VERILATOR_ROOT/bin
+
+Building Testbench
+------------------
+
+To build with default settings:
+
+ make build
+
+To enable VCD dump into `dump.vcd`. Note that the dumping support is compiled
+into the testbench binary and hence you need to rebuild to turn it on and off.
+
+ make build cflags='-DVCDTRACE=1'
+
+To build with Verilator prior to 3.922:
+
+ make build vflags_extra='--trace +define+DISABLE_SV_ASSERTION=1'
+
+Running
+-------
+
+To run the supported regression test suite:
+
+ make regression
+
+To run a full regression test suite (including e.g. floating-point ISA tests):
+
+ make regression isa_test_patts='*'
+
+To run a single test:
+
+ # either run as a regression suite of one test
+ make regression isa_tests=rv32ui-p-xori
+
+ # or run as a single test
+ make test-rv32ui-p-xori
+

verilator/sim.cpp

@@ -0,0 +1,102 @@
+/*
+Copyright 2018 Tomas Brabec
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include "Vtb_verilator.h"
+#include <verilated.h>
+
+#if VM_TRACE
+#include <verilated_vcd_c.h>
+#endif
+
+vluint64_t simtime = 0; // Current simulation time
+ // This is a 64-bit integer to reduce wrap over issues and
+ // allow modulus. You can also use a double, if you wish.
+
+double sc_time_stamp () { // Called by $time in Verilog
+	return simtime; // converts to double, to match
+ // what SystemC does
+}
+
+int main(int argc, char **argv, char **env) {
+	Verilated::commandArgs(argc, argv);
+	Vtb_verilator* top = new Vtb_verilator;
+	int cnt;
+	simtime = 0;
+
+#if VM_TRACE
+	Verilated::traceEverOn(true);
+ VerilatedVcdC* tfp = new VerilatedVcdC;
+#if VCDTRACE
+	top->trace (tfp, 99);
+ tfp->open ("dump.vcd");
+#endif
+#endif
+
+	// reset
+	top->rst_n = 1;
+	top->clk = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 1;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+
+	while (!Verilated::gotFinish() && cnt < (1 << 15)) {
+ top->clk = 1;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ top->clk = 0;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ cnt++;
+	}
+	delete top;
+
+#if VM_TRACE
+#if VCDTRACE
+	tfp->close();
+#endif
+	delete tfp;
+#endif
+
+	if (!Verilated::gotFinish()) {
+ printf("Simulation time out! Forced stop ...\n");
+ return 1;
+	} else {
+#if VM_COVERAGE
+ VerilatedCov::write("coverage.dat");
+#endif // VM_COVERAGE
+ return 0;
+	}
+}

fpga/common.mk

@@ -7,7 +7,7 @@
 # - CONFIG
 # - FPGA_DIR
 
-CORE = e201
+CORE = e203
 PATCHVERILOG ?= ""
 
 
@@ -25,8 +25,7 @@ install:
 	sed -i '1i\`define FPGA_SOURCE\' ${INSTALL_RTL}/core/${CORE}_defines.v
 
 EXTRA_FPGA_VSRCS := 
-verilog := $(wildcard ${INSTALL_RTL}/*/*.v)
-verilog += $(wildcard ${INSTALL_RTL}/*.v)
+verilog =$(wildcard ${INSTALL_RTL}/*/*.v ${INSTALL_RTL}/*.v)
 
 
 # Build .mcs
@@ -42,7 +41,7 @@ bit : install
 
 
 .PHONY: setup
-setup: 
+setup: install
 	BASEDIR=${base_dir} VSRCS="$(verilog)" EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) setup
 
 

rtl/e203/core/e203_clkgate.v

@@ -46,7 +46,7 @@ module e203_clkgate (
 
 `ifndef FPGA_SOURCE//{
 
-reg enb;
+reg enb /*verilator clock_enable*/;
 
 always@(*)
  if (!clk_in)

rtl/e203/general/sirv_sim_ram.v

@@ -48,7 +48,7 @@ module sirv_sim_ram
  output [DW-1:0] dout
 );
 
- reg [DW-1:0] mem_r [0:DP-1];
+ reg [0:DP-1] [DW-1:0] mem_r;
  reg [AW-1:0] addr_r;
  wire [MW-1:0] wen;
  wire ren;

sirv-e-sdk/Makefile

@@ -108,20 +108,28 @@ toolchain_prefix := $(toolchain_builddir)/prefix
 
 RISCV_PATH ?= $(toolchain_prefix)
 
+ifeq ($(GCCVER),)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-ar)
+endif
+
 ifeq ($(GCCVER),6)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
 endif
 
 ifeq ($(GCCVER),7)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
 endif
 
 PATH := $(abspath $(RISCV_PATH)/bin):$(PATH)
@@ -198,6 +206,7 @@ PROGRAM_DIR = software/$(PROGRAM)
 PROGRAM_ELF = software/$(PROGRAM)/$(PROGRAM)
 
 .PHONY: software_clean
+clean: software_clean
 software_clean:
 	$(MAKE) -C $(PROGRAM_DIR) BSP_BASE=$(abspath bsp) BOARD=$(BOARD) clean
 

verilator/Makefile

@@ -0,0 +1,78 @@
+# Copyright 2018 Tomas Brabec
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# 
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+SHELL=bash
+
+vdir = ../rtl/e203
+vsrc = tb_verilator.v $(foreach d,$(wildcard $(vdir)/*),$(wildcard $(d)/*.*v*))
+csrc = sim.cpp
+cflags =
+objdir = obj
+obj = $(csrc:%.cpp=%)
+vflags = $(if $(cflags),-CFLAGS $(cflags)) --cc --exe --Mdir $(objdir) +incdir+$(vdir)/core +incdir+$(vdir)/perips \
+ --top-module tb_verilator \
+ -Wno-WIDTH -Wno-UNOPTFLAT -Wno-CASEINCOMPLETE -Wno-LITENDIAN
+vflags_extra = --trace
+
+isa_test_patts ?= rv32ui* rv32um* rv32uc* rv32ua* rv32mi*
+isa_test_dir ?= ../riscv-tools/riscv-tests/isa/generated
+isa_tests ?= $(basename $(notdir $(wildcard $(foreach p,$(isa_test_patts),$(isa_test_dir)/$(p).verilog))))
+
+
+.PHONY: help
+help:
+	@echo -e "Usage:\n\tmake [ooptions] [target] [<variable>=<value>]"
+	@echo -e "\nTargets:"
+	@echo -e " help prints this help message"
+	@echo -e " list-tests lists available ISA tests"
+	@echo -e " build creates a testbench binary ($(objdir)/$(obj))"
+	@echo -e " regression runs all tests listed by 'list-tests'"
+	@echo -e " test-<name> runs a single test"
+	@echo -e " clean delete all outputs"
+	@echo -e "\nVariables:"
+	@echo -e " isa_test_patts space separated list of patterns of ISA tests"
+	@echo -e " (actual: '$(isa_test_patts)')"
+	@echo -e " isa_tests space separated list of tests to run for 'regression',"
+	@echo -e " use 'make list' to display the corresponding list"
+	@echo -e " cflags extra C++ compiler flags"
+	@echo -e " use cflags='-DVCDTRACE=1' to enable VCD dump into dump.vcd file."
+	@echo -e "\nExamples:"
+	@echo -e " make build test-rv32ui-p-xori"
+	@echo -e " make regression isa_tests=rv32ui-p-xori"
+	@echo -e " make regression isa_patts='rv32ui*'"
+	@echo -e ""
+
+.PHONY: list-tests list
+list list-tests:
+	@echo $(isa_tests)
+
+
+.PHONY: all build
+all build: $(objdir)/$(obj)
+
+$(objdir)/$(obj): $(vsrc) $(csrc)
+	verilator $(vflags) $(vflags_extra) -o $(notdir $(obj)) $(csrc) $(vsrc)
+	make -C $(objdir) -f Vtb_verilator.mk
+
+.PHONY: clean
+clean:
+	rm -rf $(objdir) results dump.vcd && for f in *.verilog; do if [ -L $${f} ]; then unlink $${f}; fi; done
+
+.PHONY: regression
+regression: $(isa_tests:%=test-%)
+
+test-%: $(isa_test_dir)/%.verilog
+	@test -e $*.verilog || ln -s $<
+	@mkdir -p results && echo "Running '$*' test ..." && $(objdir)/$(obj) +TESTCASE=$* > results/$*.log
+

verilator/README.md

@@ -0,0 +1,100 @@
+ISA Tests under Verilator
+=========================
+
+This folder contains a Verilator testbench to exercise RTL against ISA
+[riscv-tests](https://github.com/riscv/riscv-tests).
+
+The testbench was tested with Verilator 3.924 and should work out of the box
+with 3.922 (as the 1st version supporting SV `assert property`). For earlier
+versions one needs to verilate with `+define+DISABLE_SV_ASSERTIONS=1`.
+
+Limitations
+-----------
+
+- Regressions support pre-compiled versions of [riscv-tests](https://github.com/riscv/riscv-tests)
+ available in `riscv-tools/riscv-tests/isa/generated` folder.
+
+- Hard-coded number of clock cycles. The C++ testbench forces the simulation
+ to stop after 1024 cycles. This may be changed in `sim.cpp`.
+
+- The RTL code needs to be verilated with `--trace` option and a VCD trace
+ instance created in the C++ testbench. Otherwise the simulation does not
+ work/converge.
+
+Installing Verilator
+--------------------
+
+### Installing Packaged Version ###
+
+Instructions from https://github.com/ucb-bar/riscv-sodor
+
+- Ubuntu 17.04 and on
+
+ sudo apt install pkg-config verilator
+
+- Ubuntu 16.04 and earlier
+
+ sudo apt install pkg-config
+ wget http://mirrors.kernel.org/ubuntu/pool/universe/v/verilator/verilator_3.900-1_amd64.deb
+ sudo dpkg -i verilator_3.900-1_amd64.deb
+
+### Building from Source ###
+
+Instructions adapted from https://github.com/ucb-bar/riscv-sodor
+
+ # install packages needed for compilation
+ sudo apt-get install make autoconf g++ flex bison libfl-dev
+
+ # optionally install GtkWave
+ sudo apt-get install gtkwave
+
+ # obtain a released version
+ # (alternatively clone a git repo: http://git.veripool.org/git/verilator)
+ wget https://www.veripool.org/ftp/verilator-3.924.tgz
+ tar -xzf verilator-3.924.tgz
+
+ # compile
+ # (when intending to install, consider using ./configure --prefix=<path>)
+ cd verilator*
+ unset VERILATOR_ROOT
+ ./configure && make
+
+ # set environment
+ export VERILATOR_ROOT=$PWD
+ export PATH=$PATH:$VERILATOR_ROOT/bin
+
+Building Testbench
+------------------
+
+To build with default settings:
+
+ make build
+
+To enable VCD dump into `dump.vcd`. Note that the dumping support is compiled
+into the testbench binary and hence you need to rebuild to turn it on and off.
+
+ make build cflags='-DVCDTRACE=1'
+
+To build with Verilator prior to 3.922:
+
+ make build vflags_extra='--trace +define+DISABLE_SV_ASSERTION=1'
+
+Running
+-------
+
+To run the supported regression test suite:
+
+ make regression
+
+To run a full regression test suite (including e.g. floating-point ISA tests):
+
+ make regression isa_test_patts='*'
+
+To run a single test:
+
+ # either run as a regression suite of one test
+ make regression isa_tests=rv32ui-p-xori
+
+ # or run as a single test
+ make test-rv32ui-p-xori
+

verilator/sim.cpp

@@ -0,0 +1,102 @@
+/*
+Copyright 2018 Tomas Brabec
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include "Vtb_verilator.h"
+#include <verilated.h>
+
+#if VM_TRACE
+#include <verilated_vcd_c.h>
+#endif
+
+vluint64_t simtime = 0; // Current simulation time
+ // This is a 64-bit integer to reduce wrap over issues and
+ // allow modulus. You can also use a double, if you wish.
+
+double sc_time_stamp () { // Called by $time in Verilog
+	return simtime; // converts to double, to match
+ // what SystemC does
+}
+
+int main(int argc, char **argv, char **env) {
+	Verilated::commandArgs(argc, argv);
+	Vtb_verilator* top = new Vtb_verilator;
+	int cnt;
+	simtime = 0;
+
+#if VM_TRACE
+	Verilated::traceEverOn(true);
+ VerilatedVcdC* tfp = new VerilatedVcdC;
+#if VCDTRACE
+	top->trace (tfp, 99);
+ tfp->open ("dump.vcd");
+#endif
+#endif
+
+	// reset
+	top->rst_n = 1;
+	top->clk = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 1;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+
+	while (!Verilated::gotFinish() && cnt < (1 << 15)) {
+ top->clk = 1;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ top->clk = 0;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ cnt++;
+	}
+	delete top;
+
+#if VM_TRACE
+#if VCDTRACE
+	tfp->close();
+#endif
+	delete tfp;
+#endif
+
+	if (!Verilated::gotFinish()) {
+ printf("Simulation time out! Forced stop ...\n");
+ return 1;
+	} else {
+#if VM_COVERAGE
+ VerilatedCov::write("coverage.dat");
+#endif // VM_COVERAGE
+ return 0;
+	}
+}

fpga/common.mk

@@ -7,7 +7,7 @@
 # - CONFIG
 # - FPGA_DIR
 
-CORE = e201
+CORE = e203
 PATCHVERILOG ?= ""
 
 
@@ -25,8 +25,7 @@ install:
 	sed -i '1i\`define FPGA_SOURCE\' ${INSTALL_RTL}/core/${CORE}_defines.v
 
 EXTRA_FPGA_VSRCS := 
-verilog := $(wildcard ${INSTALL_RTL}/*/*.v)
-verilog += $(wildcard ${INSTALL_RTL}/*.v)
+verilog =$(wildcard ${INSTALL_RTL}/*/*.v ${INSTALL_RTL}/*.v)
 
 
 # Build .mcs
@@ -42,7 +41,7 @@ bit : install
 
 
 .PHONY: setup
-setup: 
+setup: install
 	BASEDIR=${base_dir} VSRCS="$(verilog)" EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) setup
 
 

rtl/e203/core/e203_clkgate.v

@@ -46,7 +46,7 @@ module e203_clkgate (
 
 `ifndef FPGA_SOURCE//{
 
-reg enb;
+reg enb /*verilator clock_enable*/;
 
 always@(*)
  if (!clk_in)

rtl/e203/general/sirv_sim_ram.v

@@ -48,7 +48,7 @@ module sirv_sim_ram
  output [DW-1:0] dout
 );
 
- reg [DW-1:0] mem_r [0:DP-1];
+ reg [0:DP-1] [DW-1:0] mem_r;
  reg [AW-1:0] addr_r;
  wire [MW-1:0] wen;
  wire ren;

sirv-e-sdk/Makefile

@@ -108,20 +108,28 @@ toolchain_prefix := $(toolchain_builddir)/prefix
 
 RISCV_PATH ?= $(toolchain_prefix)
 
+ifeq ($(GCCVER),)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv64-unknown-elf-ar)
+endif
+
 ifeq ($(GCCVER),6)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv32-unknown-elf-ar)
 endif
 
 ifeq ($(GCCVER),7)
-RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
-RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
-RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
-RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
+RISCV_GCC ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
+RISCV_GXX ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
+RISCV_OBJDUMP ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
+RISCV_GDB ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
+RISCV_AR ?= $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
 endif
 
 PATH := $(abspath $(RISCV_PATH)/bin):$(PATH)
@@ -198,6 +206,7 @@ PROGRAM_DIR = software/$(PROGRAM)
 PROGRAM_ELF = software/$(PROGRAM)/$(PROGRAM)
 
 .PHONY: software_clean
+clean: software_clean
 software_clean:
 	$(MAKE) -C $(PROGRAM_DIR) BSP_BASE=$(abspath bsp) BOARD=$(BOARD) clean
 

verilator/Makefile

@@ -0,0 +1,78 @@
+# Copyright 2018 Tomas Brabec
+# 
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# 
+# http://www.apache.org/licenses/LICENSE-2.0
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+SHELL=bash
+
+vdir = ../rtl/e203
+vsrc = tb_verilator.v $(foreach d,$(wildcard $(vdir)/*),$(wildcard $(d)/*.*v*))
+csrc = sim.cpp
+cflags =
+objdir = obj
+obj = $(csrc:%.cpp=%)
+vflags = $(if $(cflags),-CFLAGS $(cflags)) --cc --exe --Mdir $(objdir) +incdir+$(vdir)/core +incdir+$(vdir)/perips \
+ --top-module tb_verilator \
+ -Wno-WIDTH -Wno-UNOPTFLAT -Wno-CASEINCOMPLETE -Wno-LITENDIAN
+vflags_extra = --trace
+
+isa_test_patts ?= rv32ui* rv32um* rv32uc* rv32ua* rv32mi*
+isa_test_dir ?= ../riscv-tools/riscv-tests/isa/generated
+isa_tests ?= $(basename $(notdir $(wildcard $(foreach p,$(isa_test_patts),$(isa_test_dir)/$(p).verilog))))
+
+
+.PHONY: help
+help:
+	@echo -e "Usage:\n\tmake [ooptions] [target] [<variable>=<value>]"
+	@echo -e "\nTargets:"
+	@echo -e " help prints this help message"
+	@echo -e " list-tests lists available ISA tests"
+	@echo -e " build creates a testbench binary ($(objdir)/$(obj))"
+	@echo -e " regression runs all tests listed by 'list-tests'"
+	@echo -e " test-<name> runs a single test"
+	@echo -e " clean delete all outputs"
+	@echo -e "\nVariables:"
+	@echo -e " isa_test_patts space separated list of patterns of ISA tests"
+	@echo -e " (actual: '$(isa_test_patts)')"
+	@echo -e " isa_tests space separated list of tests to run for 'regression',"
+	@echo -e " use 'make list' to display the corresponding list"
+	@echo -e " cflags extra C++ compiler flags"
+	@echo -e " use cflags='-DVCDTRACE=1' to enable VCD dump into dump.vcd file."
+	@echo -e "\nExamples:"
+	@echo -e " make build test-rv32ui-p-xori"
+	@echo -e " make regression isa_tests=rv32ui-p-xori"
+	@echo -e " make regression isa_patts='rv32ui*'"
+	@echo -e ""
+
+.PHONY: list-tests list
+list list-tests:
+	@echo $(isa_tests)
+
+
+.PHONY: all build
+all build: $(objdir)/$(obj)
+
+$(objdir)/$(obj): $(vsrc) $(csrc)
+	verilator $(vflags) $(vflags_extra) -o $(notdir $(obj)) $(csrc) $(vsrc)
+	make -C $(objdir) -f Vtb_verilator.mk
+
+.PHONY: clean
+clean:
+	rm -rf $(objdir) results dump.vcd && for f in *.verilog; do if [ -L $${f} ]; then unlink $${f}; fi; done
+
+.PHONY: regression
+regression: $(isa_tests:%=test-%)
+
+test-%: $(isa_test_dir)/%.verilog
+	@test -e $*.verilog || ln -s $<
+	@mkdir -p results && echo "Running '$*' test ..." && $(objdir)/$(obj) +TESTCASE=$* > results/$*.log
+

verilator/README.md

@@ -0,0 +1,100 @@
+ISA Tests under Verilator
+=========================
+
+This folder contains a Verilator testbench to exercise RTL against ISA
+[riscv-tests](https://github.com/riscv/riscv-tests).
+
+The testbench was tested with Verilator 3.924 and should work out of the box
+with 3.922 (as the 1st version supporting SV `assert property`). For earlier
+versions one needs to verilate with `+define+DISABLE_SV_ASSERTIONS=1`.
+
+Limitations
+-----------
+
+- Regressions support pre-compiled versions of [riscv-tests](https://github.com/riscv/riscv-tests)
+ available in `riscv-tools/riscv-tests/isa/generated` folder.
+
+- Hard-coded number of clock cycles. The C++ testbench forces the simulation
+ to stop after 1024 cycles. This may be changed in `sim.cpp`.
+
+- The RTL code needs to be verilated with `--trace` option and a VCD trace
+ instance created in the C++ testbench. Otherwise the simulation does not
+ work/converge.
+
+Installing Verilator
+--------------------
+
+### Installing Packaged Version ###
+
+Instructions from https://github.com/ucb-bar/riscv-sodor
+
+- Ubuntu 17.04 and on
+
+ sudo apt install pkg-config verilator
+
+- Ubuntu 16.04 and earlier
+
+ sudo apt install pkg-config
+ wget http://mirrors.kernel.org/ubuntu/pool/universe/v/verilator/verilator_3.900-1_amd64.deb
+ sudo dpkg -i verilator_3.900-1_amd64.deb
+
+### Building from Source ###
+
+Instructions adapted from https://github.com/ucb-bar/riscv-sodor
+
+ # install packages needed for compilation
+ sudo apt-get install make autoconf g++ flex bison libfl-dev
+
+ # optionally install GtkWave
+ sudo apt-get install gtkwave
+
+ # obtain a released version
+ # (alternatively clone a git repo: http://git.veripool.org/git/verilator)
+ wget https://www.veripool.org/ftp/verilator-3.924.tgz
+ tar -xzf verilator-3.924.tgz
+
+ # compile
+ # (when intending to install, consider using ./configure --prefix=<path>)
+ cd verilator*
+ unset VERILATOR_ROOT
+ ./configure && make
+
+ # set environment
+ export VERILATOR_ROOT=$PWD
+ export PATH=$PATH:$VERILATOR_ROOT/bin
+
+Building Testbench
+------------------
+
+To build with default settings:
+
+ make build
+
+To enable VCD dump into `dump.vcd`. Note that the dumping support is compiled
+into the testbench binary and hence you need to rebuild to turn it on and off.
+
+ make build cflags='-DVCDTRACE=1'
+
+To build with Verilator prior to 3.922:
+
+ make build vflags_extra='--trace +define+DISABLE_SV_ASSERTION=1'
+
+Running
+-------
+
+To run the supported regression test suite:
+
+ make regression
+
+To run a full regression test suite (including e.g. floating-point ISA tests):
+
+ make regression isa_test_patts='*'
+
+To run a single test:
+
+ # either run as a regression suite of one test
+ make regression isa_tests=rv32ui-p-xori
+
+ # or run as a single test
+ make test-rv32ui-p-xori
+

verilator/sim.cpp

@@ -0,0 +1,102 @@
+/*
+Copyright 2018 Tomas Brabec
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include "Vtb_verilator.h"
+#include <verilated.h>
+
+#if VM_TRACE
+#include <verilated_vcd_c.h>
+#endif
+
+vluint64_t simtime = 0; // Current simulation time
+ // This is a 64-bit integer to reduce wrap over issues and
+ // allow modulus. You can also use a double, if you wish.
+
+double sc_time_stamp () { // Called by $time in Verilog
+	return simtime; // converts to double, to match
+ // what SystemC does
+}
+
+int main(int argc, char **argv, char **env) {
+	Verilated::commandArgs(argc, argv);
+	Vtb_verilator* top = new Vtb_verilator;
+	int cnt;
+	simtime = 0;
+
+#if VM_TRACE
+	Verilated::traceEverOn(true);
+ VerilatedVcdC* tfp = new VerilatedVcdC;
+#if VCDTRACE
+	top->trace (tfp, 99);
+ tfp->open ("dump.vcd");
+#endif
+#endif
+
+	// reset
+	top->rst_n = 1;
+	top->clk = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 0;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+	top->rst_n = 1;
+	top->eval();
+#if VM_TRACE && VCDTRACE
+	tfp->dump(simtime);
+#endif
+	simtime++;
+
+	while (!Verilated::gotFinish() && cnt < (1 << 15)) {
+ top->clk = 1;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ top->clk = 0;
+ top->eval();
+#if VM_TRACE && VCDTRACE
+ tfp->dump(simtime);
+#endif
+ simtime++;
+ cnt++;
+	}
+	delete top;
+
+#if VM_TRACE
+#if VCDTRACE
+	tfp->close();
+#endif
+	delete tfp;
+#endif
+
+	if (!Verilated::gotFinish()) {
+ printf("Simulation time out! Forced stop ...\n");
+ return 1;
+	} else {
+#if VM_COVERAGE
+ VerilatedCov::write("coverage.dat");
+#endif // VM_COVERAGE
+ return 0;
+	}
+}