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@VLSIDA

VLSI Design & Automation Group

UC Santa Cruz VLSI Design and Automation research lab

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  1. OpenRAMOpenRAMPublic

    An open-source static random access memory (SRAM) compiler.

    Python 1.1k 277

  2. chip-tutorialschip-tutorialsPublic

    Python 28 10

  3. OpenROAD-flow-scriptsOpenROAD-flow-scriptsPublic

    Forked from The-OpenROAD-Project/OpenROAD-flow-scripts

    OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

    Verilog 1

  4. OpenROADOpenROADPublic

    Forked from The-OpenROAD-Project/OpenROAD

    OpenROAD's unified application implementing an RTL-to-GDS Flow

    Verilog 7

  5. HighTideHighTidePublic

    Verilog 36 13

  6. cocotbext-amscocotbext-amsPublic

    An analog simulator bridge for cocotb — open-source mixed-signal co-simulation

    Python 11 3

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