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Databaseprocess - #32
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zdobersek
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Mar 11, 2016
LGTM. |
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Mar 11, 2016
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Mar 7, 2017
…s and zero reg https://bugs.webkit.org/show_bug.cgi?id=168527 Reviewed by Filip Pizlo. Added support for data processing 1 source instructions like rbit, rev, clz and cls. Added support for the FP conditional select instruction, fcsel. Consolidated the two classes for handling dmb instructions into one class. Fixed the instruction selection mask in the integer conditional select class, A64DOpcodeConditionalSelect. Fixed the processing of extract instruction (extr) including the rotate right (ror) pseudo instruction. Changed the printing of x31 and w31 to xzr and wzr as operands according to the spec. Added support for common pseudo instructions. This includes: - mvn x1, X2 in place of orn x1, xzr, x2 - lsl x3, x4, #count in place of ubfiz x3, x4, #count, #count - smull x5, w6, w7 in place of smaddl x5, w6, w7, XZR - More understandable mov x8, #-304 in place of movn x8, #0x12f - Eliminated xzr from register index loads and stores, outputing ldr x10, [x11] instead of ldr x10, [x11, xzr] Changed the move wide instructions to use hex literals for movz and movk. This makes it much easier to decifer sequences of wide moves for large literals. Before After movz x17, #26136 movz x17, #0x6618 movk x17, #672, lsl #16 movk x17, #0x2a0, lsl #16 movk x17, #1, lsl #32 movk x17, #0x1, lsl #32 Verified that all instructions currently generated by the JSC stress tests are disassembled. * disassembler/ARM64/A64DOpcode.cpp: (JSC::ARM64Disassembler::A64DOpcodeBitfield::format): (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::format): (JSC::ARM64Disassembler::A64DOpcodeDataProcessing2Source::format): (JSC::ARM64Disassembler::A64DOpcodeDataProcessing3Source::format): (JSC::ARM64Disassembler::A64DOpcodeExtract::format): (JSC::ARM64Disassembler::A64DOpcodeFloatingPointConditionalSelect::format): (JSC::ARM64Disassembler::A64DOpcodeFloatingPointIntegerConversions::format): (JSC::ARM64Disassembler::A64DOpcodeDmb::format): (JSC::ARM64Disassembler::A64DOpcodeLoadStoreImmediate::format): (JSC::ARM64Disassembler::A64DOpcodeLoadStoreRegisterOffset::format): (JSC::ARM64Disassembler::A64DOpcodeLoadStoreRegisterPair::format): (JSC::ARM64Disassembler::A64DOpcodeLoadStoreUnsignedImmediate::format): (JSC::ARM64Disassembler::A64DOpcodeLogicalShiftedRegister::format): (JSC::ARM64Disassembler::A64DOpcodeMoveWide::format): (JSC::ARM64Disassembler::A64DOpcodeDmbIsh::format): Deleted. (JSC::ARM64Disassembler::A64DOpcodeDmbIshSt::format): Deleted. * disassembler/ARM64/A64DOpcode.h: (JSC::ARM64Disassembler::A64DOpcode::appendSignedImmediate64): (JSC::ARM64Disassembler::A64DOpcode::appendUnsignedHexImmediate): (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::opName): (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::sBit): (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::opCode): (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::opCode2): (JSC::ARM64Disassembler::A64DOpcodeDataProcessing1Source::opNameIndex): (JSC::ARM64Disassembler::A64DOpcodeDataProcessing3Source::opName): (JSC::ARM64Disassembler::A64DOpcodeFloatingPointConditionalSelect::opName): (JSC::ARM64Disassembler::A64DOpcodeFloatingPointConditionalSelect::condition): (JSC::ARM64Disassembler::A64DOpcodeDmb::option): (JSC::ARM64Disassembler::A64DOpcodeDmb::crM): (JSC::ARM64Disassembler::A64DOpcodeLogicalShiftedRegister::isMov): (JSC::ARM64Disassembler::A64DOpcodeDmbIsh::opName): Deleted. (JSC::ARM64Disassembler::A64DOpcodeDmbIshSt::opName): Deleted. git-svn-id: http://svn.webkit.org/repository/webkit/trunk@212592 268f45cc-cd09-0410-ab3c-d52691b4dbfc
zdobersek pushed a commit
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Mar 20, 2017
https://bugs.webkit.org/show_bug.cgi?id=168685 Reviewed by Mark Lam. This patch extends the previous Air disassembler to print the DFG and B3 nodes belonging to particular Air instructions. The algorithm I'm using to do this is not perfect. For example, it won't try to print the entire DFG/B3 graph. It'll just print the related nodes for particular Air instructions. We can make the algorithm more sophisticated as we get more experience looking at these IR dumps and get a better feel for what we want out of them. This is an example of the output: ... ... 200:<!0:-> InvalidationPoint(MustGen, W:SideState, Exits, bc#28, exit: bc#25 --> _getEntry#DlGw2r:<0x10276f980> bc#37) Void @54 = Patchpoint(@29:ColdAny, @29:ColdAny, @53:ColdAny, DFG:@200, generator = 0x1015d6c18, earlyClobbered = [], lateClobbered = [], usedRegisters = [%r0, %r19, %r20, %r21, %r22, %fp], resultConstraint = WarmAny, ExitsSideways|WritesPinned|ReadsPinned|Reads:Top) Patch &Patchpoint2, %r20, %r20, %r0, @54 76:< 6:-> GetByOffset(KnownCell:@44, KnownCell:@44, JS|UseAsOther, Array, id3{_elementData}, 2, inferredType = Object, R:NamedProperties(3), Exits, bc#37) predicting Array Int64 @57 = Load(@29, DFG:@76, offset = 32, ControlDependent|Reads:100...101) Move 32(%r20), %r5, @57 0x389cc9ac0: ldur x5, [x20, #32] 115:<!0:-> CheckStructure(Cell:@76, MustGen, [0x1027eae20:[Array, {}, ArrayWithContiguous, Proto:0x1027e0140]], R:JSCell_structureID, Exits, bc#46) Int32 @58 = Load(@57, DFG:@115, ControlDependent|Reads:16...17) Move32 (%r5), %r1, @58 0x389cc9ac4: ldur w1, [x5] Int32 @59 = Const32(DFG:@115, 92) Int32 @60 = NotEqual(@58, $92(@59), DFG:@115) Void @61 = Check(@60:WarmAny, @57:ColdAny, @29:ColdAny, @29:ColdAny, @53:ColdAny, @57:ColdAny, DFG:@115, generator = 0x1057991e0, earlyClobbered = [], lateClobbered = [], usedRegisters = [%r0, %r5, %r19, %r20, %r21, %r22, %fp], ExitsSideways|Reads:Top) Patch &Branch32(3,SameAsRep)1, NotEqual, %r1, $92, %r5, %r20, %r20, %r0, %r5, @61 0x389cc9ac8: cmp w1, #92 0x389cc9acc: b.ne 0x389cc9dac 117:< 2:-> GetButterfly(Cell:@76, Storage|PureInt, R:JSObject_butterfly, Exits, bc#46) Int64 @64 = Load(@57, DFG:@117, offset = 8, ControlDependent|Reads:24...25) Move 8(%r5), %r4, @64 0x389cc9ad0: ldur x4, [x5, #8] 79:< 2:-> GetArrayLength(KnownCell:@76, Untyped:@117, JS|PureInt|UseAsInt, Nonboolint32, Contiguous+OriginalArray+InBounds+AsIs, R:Butterfly_publicLength, Exits, bc#46) Int32 @67 = Load(@64, DFG:@79, offset = -8, ControlDependent|Reads:3...4) Move32 -8(%r4), %r2, @67 0x389cc9ad4: ldur w2, [x4, #-8] 192:< 1:-> JSConstant(JS|PureInt, Nonboolint32, Int32: -1, bc#0) Int32 @68 = Const32(DFG:@192, -1) Move $0xffffffffffffffff, %r1, $-1(@68) 0x389cc9ad8: mov x1, #-1 83:<!2:-> ArithAdd(Int32:Kill:@79, Int32:Kill:@192, Number|MustGen|PureInt|UseAsInt, Int32, Unchecked, Exits, bc#55) Int32 @69 = Add(@67, $-1(@68), DFG:@83) Add32 %r2, %r1, %r1, @69 0x389cc9adc: add w1, w2, w1 86:< 3:-> BitAnd(Check:Int32:@71, Int32:Kill:@83, Int32|UseAsOther|UseAsInt|ReallyWantsInt, Int32, Exits, bc#60) Int32 @70 = Below(@53, $-281474976710656(@15), DFG:@86) Void @71 = Check(@70:WarmAny, @53:ColdAny, @29:ColdAny, @29:ColdAny, @53:ColdAny, @69:ColdAny, DFG:@86, generator = 0x105799370, earlyClobbered = [], lateClobbered = [], usedRegisters = [%r0, %r1, %r2, %r4, %r5, %r19, %r20, %r21, %r22, %fp], ExitsSideways|Reads:Top) Patch &Branch64(3,SameAsRep)0, Below, %r0, %r22, %r0, %r20, %r20, %r0, %r1, @71 0x389cc9ae0: cmp x0, x22 0x389cc9ae4: b.lo 0x389cc9dc0 Int32 @72 = Trunc(@53, DFG:@86) Int32 @73 = BitAnd(@69, @72, DFG:@86) And32 %r1, %r0, %r1, @73 0x389cc9ae8: and w1, w1, w0 16:<!0:-> PutStack(KnownInt32:@71, MustGen, loc27, machine:loc3, FlushedInt32, W:Stack(-28), bc#19) Int32 @72 = Trunc(@53, DFG:@86) Int64 @11 = SlotBase(stack0) Void @76 = Store(@72, @11, DFG:@16, offset = 32, ControlDependent|Writes:94...95) Move32 %r0, -64(%fp), @76 0x389cc9aec: stur w0, [fp, #-64] 12:<!0:-> PutStack(Untyped:@86, MustGen, loc28, machine:loc4, FlushedJSValue, W:Stack(-29), bc#19) Int64 @77 = ZExt32(@73, DFG:@12) Int64 @78 = Add(@77, $-281474976710656(@15), DFG:@12) Add64 %r1, %r22, %r3, @78 0x389cc9af0: add x3, x1, x22 Int64 @11 = SlotBase(stack0) Void @81 = Store(@78, @11, DFG:@12, offset = 24, ControlDependent|Writes:95...96) Move %r3, -72(%fp), @81 0x389cc9af4: stur x3, [fp, #-72] 10:<!0:-> PutStack(KnownInt32:@46, MustGen, loc29, machine:loc5, FlushedInt32, W:Stack(-30), bc#19) Int32 @82 = Trunc(@24, DFG:@10) Int64 @11 = SlotBase(stack0) Void @85 = Store(@82, @11, DFG:@10, offset = 16, ControlDependent|Writes:96...97) Move32 %r21, -80(%fp), @85 0x389cc9af8: stur w21, [fp, #-80] 129:<!10:-> GetByVal(KnownCell:Kill:@76, Int32:Kill:@86, Untyped:Kill:@117, JS|MustGen|UseAsOther, FinalOther, Contiguous+OriginalArray+OutOfBounds+AsIs, R:World, W:Heap, Exits, ClobbersExit, bc#19) predicting FinalOther Int32 @89 = AboveEqual(@73, @67, DFG:@129) Void @90 = Branch(@89, DFG:@129, Terminal) Branch32 AboveOrEqual, %r1, %r2, @90 0x389cc9afc: cmp w1, w2 0x389cc9b00: b.hs 0x389cc9bec ... ... * b3/air/AirDisassembler.cpp: (JSC::B3::Air::Disassembler::dump): * b3/air/AirDisassembler.h: * ftl/FTLCompile.cpp: (JSC::FTL::compile): * ftl/FTLLowerDFGToB3.cpp: (JSC::FTL::DFG::LowerDFGToB3::lower): (JSC::FTL::DFG::LowerDFGToB3::lowInt32): (JSC::FTL::DFG::LowerDFGToB3::lowCell): (JSC::FTL::DFG::LowerDFGToB3::lowBoolean): (JSC::FTL::DFG::LowerDFGToB3::lowJSValue): git-svn-id: http://svn.webkit.org/repository/webkit/trunk@213233 268f45cc-cd09-0410-ab3c-d52691b4dbfc
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Changes required to launch WPEDatabaseProcess.