ARROW-18162: [C++] Add Arm SVE compiler options - #14515

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ARROW-18162: [C++] Add Arm SVE compiler options#14515
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As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with matched vector size. Otherwise, the code behaviour is undefined.
E.g., cmake -DARROW_SIMD_LEVEL=SVE256 ..
According macro ARROW_HAVE_SVE256 and cmake variable are defined.

We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., cmake -DARROW_SIMD_LEVEL=SVE ..

This PR also removes some unused Arm64 arch options.

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https://issues.apache.org/jira/browse/ARROW-18162

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⚠️ Ticket has not been started in JIRA, please click 'Start Progress'.

pitrou
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?

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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?

Yes. SVE may be better when longer vector size is beneficial, or to leverage operations (e.g, scatter/gather) not availble in NEON.

cyb70289
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Comment threaddev/tasks/conda-recipes/arrow-cpp/build-pyarrow.sh Outdated
@cyb70289
ARROW-18162: [C++] Add Arm SVE compiler options
aa8ee3e
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with that vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
@cyb70289
Remove ARROW_ARMV8_ARCH cmake option
f99b57a
@cyb70289

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@github-actions crossbow submit conda-{linux,osx}-*

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Unable to match any tasks for `conda-{linux,osx}-*`
The Archery job run can be found at: https://github.com/apache/arrow/actions/runs/3360036059

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@github-actions crossbow submit conda-linux-*

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Revision: f99b57a

Submitted crossbow builds: ursacomputing/crossbow @ actions-19dd1864f2

TaskStatus
conda-linux-gcc-py310-arm64Azure
conda-linux-gcc-py310-cpuAzure
conda-linux-gcc-py310-cudaAzure
conda-linux-gcc-py310-ppc64leAzure
conda-linux-gcc-py37-arm64Azure
conda-linux-gcc-py37-cpu-r40Azure
conda-linux-gcc-py37-cpu-r41Azure
conda-linux-gcc-py37-cudaAzure
conda-linux-gcc-py37-ppc64leAzure
conda-linux-gcc-py38-arm64Azure
conda-linux-gcc-py38-cpuAzure
conda-linux-gcc-py38-cudaAzure
conda-linux-gcc-py38-ppc64leAzure
conda-linux-gcc-py39-arm64Azure
conda-linux-gcc-py39-cpuAzure
conda-linux-gcc-py39-cudaAzure
conda-linux-gcc-py39-ppc64leAzure

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@github-actions crossbow submit conda-osx-*

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Revision: f99b57a

Submitted crossbow builds: ursacomputing/crossbow @ actions-457a7b106d

TaskStatus
conda-osx-arm64-clang-py310Azure
conda-osx-arm64-clang-py37Azure
conda-osx-arm64-clang-py38Azure
conda-osx-arm64-clang-py39Azure
conda-osx-clang-py310Azure
conda-osx-clang-py37Azure
conda-osx-clang-py37-r40Azure
conda-osx-clang-py37-r41Azure
conda-osx-clang-py38Azure
conda-osx-clang-py39Azure

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conda-osx-clang-py310/py37 build error looks not related.
https://dev.azure.com/ursacomputing/crossbow/_build/results?buildId=38774&view=logs&j=cf796865-97b7-5cd1-be8e-6e00ce4fd8cf&t=88ee2fb8-46fd-5c68-fde3-1c8d31ba2a5f&l=3570

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+1 for changes

I re-ran failed jobs.

@cyb70289
cyb70289 merged commit 16fd7f3 into apache:masterNov 1, 2022
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Benchmark runs are scheduled for baseline = 2a5c773 and contender = 16fd7f3. 16fd7f3 is a master commit associated with this PR. Results will be available as each benchmark for each run completes.
Conbench compare runs links:
[Finished ⬇️0.0% ⬆️0.0%] ec2-t3-xlarge-us-east-2
[Failed ⬇️0.0% ⬆️0.0%] test-mac-arm
[Finished ⬇️0.54% ⬆️0.0%] ursa-i9-9960x
[Finished ⬇️0.32% ⬆️0.18%] ursa-thinkcentre-m75q
Buildkite builds:
[Finished] 16fd7f3f ec2-t3-xlarge-us-east-2
[Failed] 16fd7f3f test-mac-arm
[Finished] 16fd7f3f ursa-i9-9960x
[Finished] 16fd7f3f ursa-thinkcentre-m75q
[Finished] 2a5c7736 ec2-t3-xlarge-us-east-2
[Failed] 2a5c7736 test-mac-arm
[Finished] 2a5c7736 ursa-i9-9960x
[Finished] 2a5c7736 ursa-thinkcentre-m75q
Supported benchmarks:
ec2-t3-xlarge-us-east-2: Supported benchmark langs: Python, R. Runs only benchmarks with cloud = True
test-mac-arm: Supported benchmark langs: C++, Python, R
ursa-i9-9960x: Supported benchmark langs: Python, R, JavaScript
ursa-thinkcentre-m75q: Supported benchmark langs: C++, Java

@cyb70289
cyb70289 deleted the sve branch November 1, 2022 13:39
kou pushed a commit that referenced this pull request Nov 15, 2022
@cyb70289@kou
ARROW-18162: [C++] Add Arm SVE compiler options (#14515)
f63804f
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with matched vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
Authored-by: Yibo Cai <yibo.cai@arm.com>
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
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ARROW-18162: [C++] Add Arm SVE compiler options - #14515
Merged
cyb70289 merged 2 commits into
apache:masterfrom 
cyb70289:sve
Nov 1, 2022
Merged
ARROW-18162: [C++] Add Arm SVE compiler options#14515
cyb70289 merged 2 commits into
apache:masterfrom 
cyb70289:sve
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@cyb70289cyb70289
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Oct 26, 2022•

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As xsimd only supports fixed-size SVE, we have to specify vector size

explicitly on command line. And the binary can only run on hardware

with matched vector size. Otherwise, the code behaviour is undefined.

E.g., cmake -DARROW_SIMD_LEVEL=SVE256 ..

According macro ARROW_HAVE_SVE256 and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size

agnostic SVE code without specifying the vector size.

E.g., cmake -DARROW_SIMD_LEVEL=SVE ..
This PR also removes some unused Arm64 arch options.
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Oct 26, 2022

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https://issues.apache.org/jira/browse/ARROW-18162
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⚠️ Ticket has not been started in JIRA, please click 'Start Progress'.
pitrou
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
Yes. SVE may be better when longer vector size is beneficial, or to leverage operations (e.g, scatter/gather) not availble in NEON.
cyb70289
cyb70289
commented
Oct 27, 2022
View reviewed changes
Comment threaddev/tasks/conda-recipes/arrow-cpp/build-pyarrow.sh
Outdated

@cyb70289
ARROW-18162: [C++] Add Arm SVE compiler options
aa8ee3e
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with that vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
@cyb70289
Remove ARROW_ARMV8_ARCH cmake option
f99b57a
@cyb70289
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commented
Oct 31, 2022

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@github-actions crossbow submit conda-{linux,osx}-*
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Unable to match any tasks for `conda-{linux,osx}-*`
The Archery job run can be found at: https://github.com/apache/arrow/actions/runs/3360036059

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@github-actions crossbow submit conda-linux-*
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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-19dd1864f2
TaskStatus
conda-linux-gcc-py310-arm64Azure
conda-linux-gcc-py310-cpuAzure
conda-linux-gcc-py310-cudaAzure
conda-linux-gcc-py310-ppc64leAzure
conda-linux-gcc-py37-arm64Azure
conda-linux-gcc-py37-cpu-r40Azure
conda-linux-gcc-py37-cpu-r41Azure
conda-linux-gcc-py37-cudaAzure
conda-linux-gcc-py37-ppc64leAzure
conda-linux-gcc-py38-arm64Azure
conda-linux-gcc-py38-cpuAzure
conda-linux-gcc-py38-cudaAzure
conda-linux-gcc-py38-ppc64leAzure
conda-linux-gcc-py39-arm64Azure
conda-linux-gcc-py39-cpuAzure
conda-linux-gcc-py39-cudaAzure
conda-linux-gcc-py39-ppc64leAzure
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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-457a7b106d
TaskStatus
conda-osx-arm64-clang-py310Azure
conda-osx-arm64-clang-py37Azure
conda-osx-arm64-clang-py38Azure
conda-osx-arm64-clang-py39Azure
conda-osx-clang-py310Azure
conda-osx-clang-py37Azure
conda-osx-clang-py37-r40Azure
conda-osx-clang-py37-r41Azure
conda-osx-clang-py38Azure
conda-osx-clang-py39Azure
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conda-osx-clang-py310/py37 build error looks not related.
https://dev.azure.com/ursacomputing/crossbow/_build/results?buildId=38774&view=logs&j=cf796865-97b7-5cd1-be8e-6e00ce4fd8cf&t=88ee2fb8-46fd-5c68-fde3-1c8d31ba2a5f&l=3570
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+1 for changes
I re-ran failed jobs.
@cyb70289
cyb70289
merged commit 16fd7f3
into
apache:masterNov 1, 2022
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Benchmark runs are scheduled for baseline = 2a5c773 and contender = 16fd7f3. 16fd7f3 is a master commit associated with this PR. Results will be available as each benchmark for each run completes.

Conbench compare runs links:

[Finished ⬇️0.0% ⬆️0.0%] ec2-t3-xlarge-us-east-2

[Failed ⬇️0.0% ⬆️0.0%] test-mac-arm

[Finished ⬇️0.54% ⬆️0.0%] ursa-i9-9960x

[Finished ⬇️0.32% ⬆️0.18%] ursa-thinkcentre-m75q

Buildkite builds:

[Finished] 16fd7f3f ec2-t3-xlarge-us-east-2

[Failed] 16fd7f3f test-mac-arm

[Finished] 16fd7f3f ursa-i9-9960x

[Finished] 16fd7f3f ursa-thinkcentre-m75q

[Finished] 2a5c7736 ec2-t3-xlarge-us-east-2

[Failed] 2a5c7736 test-mac-arm

[Finished] 2a5c7736 ursa-i9-9960x

[Finished] 2a5c7736 ursa-thinkcentre-m75q

Supported benchmarks:

ec2-t3-xlarge-us-east-2: Supported benchmark langs: Python, R. Runs only benchmarks with cloud = True

test-mac-arm: Supported benchmark langs: C++, Python, R

ursa-i9-9960x: Supported benchmark langs: Python, R, JavaScript

ursa-thinkcentre-m75q: Supported benchmark langs: C++, Java
@cyb70289
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deleted the

sve

branch
November 1, 2022 13:39
kou pushed a commit
that referenced
this pull request
Nov 15, 2022
@cyb70289@kou
ARROW-18162: [C++] Add Arm SVE compiler options (#14515)
f63804f
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with matched vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
Authored-by: Yibo Cai <yibo.cai@arm.com>
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
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, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Force GitHub README to respect dark mode\n(function() {\n var style = document.createElement('style');\n style.textContent = '\n .markdown-body {\n color-scheme: dark light;\n }\n .markdown-body pre { background: #161b22 !important; }\n .markdown-body code { background: rgba(110, 118, 129, 0.4) !important; }\n .markdown-body table th, .markdown-body table td { border-color: #30363d !important; }\n .markdown-body img { background: #0d1117; }\n .markdown-body blockquote { border-left-color: #8b949e; }\n .markdown-body hr { border-color: #30363d; }\n ';\n document.head.appendChild(style);\n})();", "GitHub Dark Mode README Fix");
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try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
ARROW-18162: [C++] Add Arm SVE compiler options - #14515
Merged
cyb70289 merged 2 commits into
apache:masterfrom 
cyb70289:sve
Nov 1, 2022
Merged
ARROW-18162: [C++] Add Arm SVE compiler options#14515
cyb70289 merged 2 commits into
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Oct 26, 2022•

edited

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As xsimd only supports fixed-size SVE, we have to specify vector size

explicitly on command line. And the binary can only run on hardware

with matched vector size. Otherwise, the code behaviour is undefined.

E.g., cmake -DARROW_SIMD_LEVEL=SVE256 ..

According macro ARROW_HAVE_SVE256 and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size

agnostic SVE code without specifying the vector size.

E.g., cmake -DARROW_SIMD_LEVEL=SVE ..
This PR also removes some unused Arm64 arch options.
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https://issues.apache.org/jira/browse/ARROW-18162
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⚠️ Ticket has not been started in JIRA, please click 'Start Progress'.
pitrou
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
Yes. SVE may be better when longer vector size is beneficial, or to leverage operations (e.g, scatter/gather) not availble in NEON.
cyb70289
cyb70289
commented
Oct 27, 2022
View reviewed changes
Comment threaddev/tasks/conda-recipes/arrow-cpp/build-pyarrow.sh
Outdated

@cyb70289
ARROW-18162: [C++] Add Arm SVE compiler options
aa8ee3e
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with that vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
@cyb70289
Remove ARROW_ARMV8_ARCH cmake option
f99b57a
@cyb70289
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Oct 31, 2022

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@github-actions crossbow submit conda-{linux,osx}-*
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Unable to match any tasks for `conda-{linux,osx}-*`
The Archery job run can be found at: https://github.com/apache/arrow/actions/runs/3360036059

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@github-actions crossbow submit conda-linux-*
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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-19dd1864f2
TaskStatus
conda-linux-gcc-py310-arm64Azure
conda-linux-gcc-py310-cpuAzure
conda-linux-gcc-py310-cudaAzure
conda-linux-gcc-py310-ppc64leAzure
conda-linux-gcc-py37-arm64Azure
conda-linux-gcc-py37-cpu-r40Azure
conda-linux-gcc-py37-cpu-r41Azure
conda-linux-gcc-py37-cudaAzure
conda-linux-gcc-py37-ppc64leAzure
conda-linux-gcc-py38-arm64Azure
conda-linux-gcc-py38-cpuAzure
conda-linux-gcc-py38-cudaAzure
conda-linux-gcc-py38-ppc64leAzure
conda-linux-gcc-py39-arm64Azure
conda-linux-gcc-py39-cpuAzure
conda-linux-gcc-py39-cudaAzure
conda-linux-gcc-py39-ppc64leAzure
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@github-actions crossbow submit conda-osx-*
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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-457a7b106d
TaskStatus
conda-osx-arm64-clang-py310Azure
conda-osx-arm64-clang-py37Azure
conda-osx-arm64-clang-py38Azure
conda-osx-arm64-clang-py39Azure
conda-osx-clang-py310Azure
conda-osx-clang-py37Azure
conda-osx-clang-py37-r40Azure
conda-osx-clang-py37-r41Azure
conda-osx-clang-py38Azure
conda-osx-clang-py39Azure
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conda-osx-clang-py310/py37 build error looks not related.
https://dev.azure.com/ursacomputing/crossbow/_build/results?buildId=38774&view=logs&j=cf796865-97b7-5cd1-be8e-6e00ce4fd8cf&t=88ee2fb8-46fd-5c68-fde3-1c8d31ba2a5f&l=3570
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+1 for changes
I re-ran failed jobs.
@cyb70289
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merged commit 16fd7f3
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apache:masterNov 1, 2022
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Benchmark runs are scheduled for baseline = 2a5c773 and contender = 16fd7f3. 16fd7f3 is a master commit associated with this PR. Results will be available as each benchmark for each run completes.

Conbench compare runs links:

[Finished ⬇️0.0% ⬆️0.0%] ec2-t3-xlarge-us-east-2

[Failed ⬇️0.0% ⬆️0.0%] test-mac-arm

[Finished ⬇️0.54% ⬆️0.0%] ursa-i9-9960x

[Finished ⬇️0.32% ⬆️0.18%] ursa-thinkcentre-m75q

Buildkite builds:

[Finished] 16fd7f3f ec2-t3-xlarge-us-east-2

[Failed] 16fd7f3f test-mac-arm

[Finished] 16fd7f3f ursa-i9-9960x

[Finished] 16fd7f3f ursa-thinkcentre-m75q

[Finished] 2a5c7736 ec2-t3-xlarge-us-east-2

[Failed] 2a5c7736 test-mac-arm

[Finished] 2a5c7736 ursa-i9-9960x

[Finished] 2a5c7736 ursa-thinkcentre-m75q

Supported benchmarks:

ec2-t3-xlarge-us-east-2: Supported benchmark langs: Python, R. Runs only benchmarks with cloud = True

test-mac-arm: Supported benchmark langs: C++, Python, R

ursa-i9-9960x: Supported benchmark langs: Python, R, JavaScript

ursa-thinkcentre-m75q: Supported benchmark langs: C++, Java
@cyb70289
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deleted the

sve

branch
November 1, 2022 13:39
kou pushed a commit
that referenced
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Nov 15, 2022
@cyb70289@kou
ARROW-18162: [C++] Add Arm SVE compiler options (#14515)
f63804f
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with matched vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
Authored-by: Yibo Cai <yibo.cai@arm.com>
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
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, 'i');
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injectUserscript("// Highlight search terms from Google/DuckDuckGo/Bing referrer\n(function() {\n var ref = document.referrer;\n var terms = [];\n \n if (ref.includes('google.com') || ref.includes('duckduckgo.com') || ref.includes('bing.com')) {\n var url = new URL(ref);\n var q = url.searchParams.get('q') || url.searchParams.get('p');\n if (q) {\n terms = q.split(/\\s+/).filter(function(t) { return t.length > 2; });\n }\n }\n \n if (terms.length === 0) return;\n \n var style = document.createElement('style');\n style.textContent = '.userscript-highlight { background: #fbbf24; color: #1a1a2e; padding: 1px 3px; border-radius: 2px; }';\n document.head.appendChild(style);\n \n function highlight(node) {\n if (node.nodeType === 3) { // text node\n var text = node.textContent;\n var found = false;\n terms.forEach(function(term) {\n var regex = new RegExp('(' + term.replace(/[.*+?^${}()|[\\]\\\\]/g, '\\\\') + ')', 'gi');\n if (regex.test(text)) {\n found = true;\n var frag = document.createDocumentFragment();\n var parts = text.split(regex);\n parts.forEach(function(part, i) {\n if (i % 2 === 0) {\n frag.appendChild(document.createTextNode(part));\n } else {\n var span = document.createElement('span');\n span.className = 'userscript-highlight';\n span.textContent = part;\n frag.appendChild(span);\n }\n });\n node.parentNode.replaceChild(frag, node);\n }\n });\n } else if (node.nodeType === 1 && node.childNodes) { // element\n var skipTags = ['SCRIPT', 'STYLE', 'NOSCRIPT', 'TEXTAREA', 'INPUT', 'SELECT'];\n if (!skipTags.includes(node.tagName)) {\n Array.from(node.childNodes).forEach(highlight);\n }\n }\n }\n \n highlight(document.body);\n \n // Re-highlight on dynamic content\n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1 || node.nodeType === 3) highlight(node);\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Highlight Search Terms");
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})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
ARROW-18162: [C++] Add Arm SVE compiler options - #14515
Merged
cyb70289 merged 2 commits into
apache:masterfrom 
cyb70289:sve
Nov 1, 2022
Merged
ARROW-18162: [C++] Add Arm SVE compiler options#14515
cyb70289 merged 2 commits into
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cyb70289:sve
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Oct 26, 2022•

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As xsimd only supports fixed-size SVE, we have to specify vector size

explicitly on command line. And the binary can only run on hardware

with matched vector size. Otherwise, the code behaviour is undefined.

E.g., cmake -DARROW_SIMD_LEVEL=SVE256 ..

According macro ARROW_HAVE_SVE256 and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size

agnostic SVE code without specifying the vector size.

E.g., cmake -DARROW_SIMD_LEVEL=SVE ..
This PR also removes some unused Arm64 arch options.
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https://issues.apache.org/jira/browse/ARROW-18162
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⚠️ Ticket has not been started in JIRA, please click 'Start Progress'.
pitrou
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Comment threadcpp/cmake_modules/SetupCxxFlags.cmake
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
Yes. SVE may be better when longer vector size is beneficial, or to leverage operations (e.g, scatter/gather) not availble in NEON.
cyb70289
cyb70289
commented
Oct 27, 2022
View reviewed changes
Comment threaddev/tasks/conda-recipes/arrow-cpp/build-pyarrow.sh
Outdated

@cyb70289
ARROW-18162: [C++] Add Arm SVE compiler options
aa8ee3e
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with that vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
@cyb70289
Remove ARROW_ARMV8_ARCH cmake option
f99b57a
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@github-actions crossbow submit conda-{linux,osx}-*
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Unable to match any tasks for `conda-{linux,osx}-*`
The Archery job run can be found at: https://github.com/apache/arrow/actions/runs/3360036059

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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-19dd1864f2
TaskStatus
conda-linux-gcc-py310-arm64Azure
conda-linux-gcc-py310-cpuAzure
conda-linux-gcc-py310-cudaAzure
conda-linux-gcc-py310-ppc64leAzure
conda-linux-gcc-py37-arm64Azure
conda-linux-gcc-py37-cpu-r40Azure
conda-linux-gcc-py37-cpu-r41Azure
conda-linux-gcc-py37-cudaAzure
conda-linux-gcc-py37-ppc64leAzure
conda-linux-gcc-py38-arm64Azure
conda-linux-gcc-py38-cpuAzure
conda-linux-gcc-py38-cudaAzure
conda-linux-gcc-py38-ppc64leAzure
conda-linux-gcc-py39-arm64Azure
conda-linux-gcc-py39-cpuAzure
conda-linux-gcc-py39-cudaAzure
conda-linux-gcc-py39-ppc64leAzure
@cyb70289
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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-457a7b106d
TaskStatus
conda-osx-arm64-clang-py310Azure
conda-osx-arm64-clang-py37Azure
conda-osx-arm64-clang-py38Azure
conda-osx-arm64-clang-py39Azure
conda-osx-clang-py310Azure
conda-osx-clang-py37Azure
conda-osx-clang-py37-r40Azure
conda-osx-clang-py37-r41Azure
conda-osx-clang-py38Azure
conda-osx-clang-py39Azure
@cyb70289
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conda-osx-clang-py310/py37 build error looks not related.
https://dev.azure.com/ursacomputing/crossbow/_build/results?buildId=38774&view=logs&j=cf796865-97b7-5cd1-be8e-6e00ce4fd8cf&t=88ee2fb8-46fd-5c68-fde3-1c8d31ba2a5f&l=3570
@cyb70289
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requested review from
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+1 for changes
I re-ran failed jobs.
@cyb70289
cyb70289
merged commit 16fd7f3
into
apache:masterNov 1, 2022
@ursabot
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Benchmark runs are scheduled for baseline = 2a5c773 and contender = 16fd7f3. 16fd7f3 is a master commit associated with this PR. Results will be available as each benchmark for each run completes.

Conbench compare runs links:

[Finished ⬇️0.0% ⬆️0.0%] ec2-t3-xlarge-us-east-2

[Failed ⬇️0.0% ⬆️0.0%] test-mac-arm

[Finished ⬇️0.54% ⬆️0.0%] ursa-i9-9960x

[Finished ⬇️0.32% ⬆️0.18%] ursa-thinkcentre-m75q

Buildkite builds:

[Finished] 16fd7f3f ec2-t3-xlarge-us-east-2

[Failed] 16fd7f3f test-mac-arm

[Finished] 16fd7f3f ursa-i9-9960x

[Finished] 16fd7f3f ursa-thinkcentre-m75q

[Finished] 2a5c7736 ec2-t3-xlarge-us-east-2

[Failed] 2a5c7736 test-mac-arm

[Finished] 2a5c7736 ursa-i9-9960x

[Finished] 2a5c7736 ursa-thinkcentre-m75q

Supported benchmarks:

ec2-t3-xlarge-us-east-2: Supported benchmark langs: Python, R. Runs only benchmarks with cloud = True

test-mac-arm: Supported benchmark langs: C++, Python, R

ursa-i9-9960x: Supported benchmark langs: Python, R, JavaScript

ursa-thinkcentre-m75q: Supported benchmark langs: C++, Java
@cyb70289
cyb70289
deleted the

sve

branch
November 1, 2022 13:39
kou pushed a commit
that referenced
this pull request
Nov 15, 2022
@cyb70289@kou
ARROW-18162: [C++] Add Arm SVE compiler options (#14515)
f63804f
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with matched vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
Authored-by: Yibo Cai <yibo.cai@arm.com>
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
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, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Strip utm_, fbclid, gclid, etc. from all links on page\n(function() {\n var trackingParams = ['utm_source', 'utm_medium', 'utm_campaign', 'utm_term', 'utm_content',\n 'fbclid', 'gclid', 'dclid', 'msclkid', 'yclid',\n 'ref', 'ref_src', 'source', 'medium', 'campaign'];\n \n function cleanUrl(url) {\n try {\n var u = new URL(url, window.location.origin);\n var changed = false;\n trackingParams.forEach(function(p) {\n if (u.searchParams.has(p)) {\n u.searchParams.delete(p);\n changed = true;\n }\n });\n return changed ? u.toString() : url;\n } catch (e) {\n return url;\n }\n }\n \n function cleanLinks() {\n document.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n \n cleanLinks();\n \n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1) {\n if (node.tagName === 'A') cleanLinks();\n node.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Remove Tracking Parameters from Links");
}
} catch(__e) { console.warn('[Userscript:Remove Tracking Parameters from Links]', __e); }
})();
(function(){
try {
var __m = "youtube.com";
var __re = new RegExp('^' + "youtube\\.com" + '

Skip to content
ARROW-18162: [C++] Add Arm SVE compiler options - #14515
Merged
cyb70289 merged 2 commits into
apache:masterfrom 
cyb70289:sve
Nov 1, 2022
Merged
ARROW-18162: [C++] Add Arm SVE compiler options#14515
cyb70289 merged 2 commits into
apache:masterfrom 
cyb70289:sve
Conversation
@cyb70289
@cyb70289cyb70289
commented
Oct 26, 2022•

edited

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As xsimd only supports fixed-size SVE, we have to specify vector size

explicitly on command line. And the binary can only run on hardware

with matched vector size. Otherwise, the code behaviour is undefined.

E.g., cmake -DARROW_SIMD_LEVEL=SVE256 ..

According macro ARROW_HAVE_SVE256 and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size

agnostic SVE code without specifying the vector size.

E.g., cmake -DARROW_SIMD_LEVEL=SVE ..
This PR also removes some unused Arm64 arch options.
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https://issues.apache.org/jira/browse/ARROW-18162
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⚠️ Ticket has not been started in JIRA, please click 'Start Progress'.
pitrou
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
Yes. SVE may be better when longer vector size is beneficial, or to leverage operations (e.g, scatter/gather) not availble in NEON.
cyb70289
cyb70289
commented
Oct 27, 2022
View reviewed changes
Comment threaddev/tasks/conda-recipes/arrow-cpp/build-pyarrow.sh
Outdated

@cyb70289
ARROW-18162: [C++] Add Arm SVE compiler options
aa8ee3e
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with that vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
@cyb70289
Remove ARROW_ARMV8_ARCH cmake option
f99b57a
@cyb70289
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@github-actions crossbow submit conda-{linux,osx}-*
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Unable to match any tasks for `conda-{linux,osx}-*`
The Archery job run can be found at: https://github.com/apache/arrow/actions/runs/3360036059

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@github-actions crossbow submit conda-linux-*
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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-19dd1864f2
TaskStatus
conda-linux-gcc-py310-arm64Azure
conda-linux-gcc-py310-cpuAzure
conda-linux-gcc-py310-cudaAzure
conda-linux-gcc-py310-ppc64leAzure
conda-linux-gcc-py37-arm64Azure
conda-linux-gcc-py37-cpu-r40Azure
conda-linux-gcc-py37-cpu-r41Azure
conda-linux-gcc-py37-cudaAzure
conda-linux-gcc-py37-ppc64leAzure
conda-linux-gcc-py38-arm64Azure
conda-linux-gcc-py38-cpuAzure
conda-linux-gcc-py38-cudaAzure
conda-linux-gcc-py38-ppc64leAzure
conda-linux-gcc-py39-arm64Azure
conda-linux-gcc-py39-cpuAzure
conda-linux-gcc-py39-cudaAzure
conda-linux-gcc-py39-ppc64leAzure
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@github-actions crossbow submit conda-osx-*
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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-457a7b106d
TaskStatus
conda-osx-arm64-clang-py310Azure
conda-osx-arm64-clang-py37Azure
conda-osx-arm64-clang-py38Azure
conda-osx-arm64-clang-py39Azure
conda-osx-clang-py310Azure
conda-osx-clang-py37Azure
conda-osx-clang-py37-r40Azure
conda-osx-clang-py37-r41Azure
conda-osx-clang-py38Azure
conda-osx-clang-py39Azure
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conda-osx-clang-py310/py37 build error looks not related.
https://dev.azure.com/ursacomputing/crossbow/_build/results?buildId=38774&view=logs&j=cf796865-97b7-5cd1-be8e-6e00ce4fd8cf&t=88ee2fb8-46fd-5c68-fde3-1c8d31ba2a5f&l=3570
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+1 for changes
I re-ran failed jobs.
@cyb70289
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merged commit 16fd7f3
into
apache:masterNov 1, 2022
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Nov 1, 2022

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Benchmark runs are scheduled for baseline = 2a5c773 and contender = 16fd7f3. 16fd7f3 is a master commit associated with this PR. Results will be available as each benchmark for each run completes.

Conbench compare runs links:

[Finished ⬇️0.0% ⬆️0.0%] ec2-t3-xlarge-us-east-2

[Failed ⬇️0.0% ⬆️0.0%] test-mac-arm

[Finished ⬇️0.54% ⬆️0.0%] ursa-i9-9960x

[Finished ⬇️0.32% ⬆️0.18%] ursa-thinkcentre-m75q

Buildkite builds:

[Finished] 16fd7f3f ec2-t3-xlarge-us-east-2

[Failed] 16fd7f3f test-mac-arm

[Finished] 16fd7f3f ursa-i9-9960x

[Finished] 16fd7f3f ursa-thinkcentre-m75q

[Finished] 2a5c7736 ec2-t3-xlarge-us-east-2

[Failed] 2a5c7736 test-mac-arm

[Finished] 2a5c7736 ursa-i9-9960x

[Finished] 2a5c7736 ursa-thinkcentre-m75q

Supported benchmarks:

ec2-t3-xlarge-us-east-2: Supported benchmark langs: Python, R. Runs only benchmarks with cloud = True

test-mac-arm: Supported benchmark langs: C++, Python, R

ursa-i9-9960x: Supported benchmark langs: Python, R, JavaScript

ursa-thinkcentre-m75q: Supported benchmark langs: C++, Java
@cyb70289
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deleted the

sve

branch
November 1, 2022 13:39
kou pushed a commit
that referenced
this pull request
Nov 15, 2022
@cyb70289@kou
ARROW-18162: [C++] Add Arm SVE compiler options (#14515)
f63804f
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with matched vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
Authored-by: Yibo Cai <yibo.cai@arm.com>
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
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, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Auto-enable theater mode on YouTube\n(function() {\n function tryTheater() {\n var btn = document.querySelector('button[aria-label=\"Theater mode\"], ytd-player #player button[title=\"Theater mode\"]');\n if (btn && !btn.classList.contains('activated')) {\n btn.click();\n }\n }\n \n // Try immediately\n tryTheater();\n \n // Try after navigation (SPA)\n var lastUrl = location.href;\n setInterval(function() {\n if (location.href !== lastUrl) {\n lastUrl = location.href;\n setTimeout(tryTheater, 500);\n }\n }, 1000);\n \n // Also try on player load\n var observer = new MutationObserver(tryTheater);\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "YouTube Theater Mode Default");
}
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})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
ARROW-18162: [C++] Add Arm SVE compiler options - #14515
Merged
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ARROW-18162: [C++] Add Arm SVE compiler options#14515
cyb70289 merged 2 commits into
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cyb70289:sve
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@cyb70289
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Oct 26, 2022•

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As xsimd only supports fixed-size SVE, we have to specify vector size

explicitly on command line. And the binary can only run on hardware

with matched vector size. Otherwise, the code behaviour is undefined.

E.g., cmake -DARROW_SIMD_LEVEL=SVE256 ..

According macro ARROW_HAVE_SVE256 and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size

agnostic SVE code without specifying the vector size.

E.g., cmake -DARROW_SIMD_LEVEL=SVE ..
This PR also removes some unused Arm64 arch options.
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Oct 26, 2022

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https://issues.apache.org/jira/browse/ARROW-18162
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⚠️ Ticket has not been started in JIRA, please click 'Start Progress'.
pitrou
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
Yes. SVE may be better when longer vector size is beneficial, or to leverage operations (e.g, scatter/gather) not availble in NEON.
cyb70289
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commented
Oct 27, 2022
View reviewed changes
Comment threaddev/tasks/conda-recipes/arrow-cpp/build-pyarrow.sh
Outdated

@cyb70289
ARROW-18162: [C++] Add Arm SVE compiler options
aa8ee3e
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with that vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
@cyb70289
Remove ARROW_ARMV8_ARCH cmake option
f99b57a
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@github-actions crossbow submit conda-{linux,osx}-*
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Unable to match any tasks for `conda-{linux,osx}-*`
The Archery job run can be found at: https://github.com/apache/arrow/actions/runs/3360036059

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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-19dd1864f2
TaskStatus
conda-linux-gcc-py310-arm64Azure
conda-linux-gcc-py310-cpuAzure
conda-linux-gcc-py310-cudaAzure
conda-linux-gcc-py310-ppc64leAzure
conda-linux-gcc-py37-arm64Azure
conda-linux-gcc-py37-cpu-r40Azure
conda-linux-gcc-py37-cpu-r41Azure
conda-linux-gcc-py37-cudaAzure
conda-linux-gcc-py37-ppc64leAzure
conda-linux-gcc-py38-arm64Azure
conda-linux-gcc-py38-cpuAzure
conda-linux-gcc-py38-cudaAzure
conda-linux-gcc-py38-ppc64leAzure
conda-linux-gcc-py39-arm64Azure
conda-linux-gcc-py39-cpuAzure
conda-linux-gcc-py39-cudaAzure
conda-linux-gcc-py39-ppc64leAzure
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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-457a7b106d
TaskStatus
conda-osx-arm64-clang-py310Azure
conda-osx-arm64-clang-py37Azure
conda-osx-arm64-clang-py38Azure
conda-osx-arm64-clang-py39Azure
conda-osx-clang-py310Azure
conda-osx-clang-py37Azure
conda-osx-clang-py37-r40Azure
conda-osx-clang-py37-r41Azure
conda-osx-clang-py38Azure
conda-osx-clang-py39Azure
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conda-osx-clang-py310/py37 build error looks not related.
https://dev.azure.com/ursacomputing/crossbow/_build/results?buildId=38774&view=logs&j=cf796865-97b7-5cd1-be8e-6e00ce4fd8cf&t=88ee2fb8-46fd-5c68-fde3-1c8d31ba2a5f&l=3570
@cyb70289
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requested review from
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+1 for changes
I re-ran failed jobs.
@cyb70289
cyb70289
merged commit 16fd7f3
into
apache:masterNov 1, 2022
@ursabot
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Benchmark runs are scheduled for baseline = 2a5c773 and contender = 16fd7f3. 16fd7f3 is a master commit associated with this PR. Results will be available as each benchmark for each run completes.

Conbench compare runs links:

[Finished ⬇️0.0% ⬆️0.0%] ec2-t3-xlarge-us-east-2

[Failed ⬇️0.0% ⬆️0.0%] test-mac-arm

[Finished ⬇️0.54% ⬆️0.0%] ursa-i9-9960x

[Finished ⬇️0.32% ⬆️0.18%] ursa-thinkcentre-m75q

Buildkite builds:

[Finished] 16fd7f3f ec2-t3-xlarge-us-east-2

[Failed] 16fd7f3f test-mac-arm

[Finished] 16fd7f3f ursa-i9-9960x

[Finished] 16fd7f3f ursa-thinkcentre-m75q

[Finished] 2a5c7736 ec2-t3-xlarge-us-east-2

[Failed] 2a5c7736 test-mac-arm

[Finished] 2a5c7736 ursa-i9-9960x

[Finished] 2a5c7736 ursa-thinkcentre-m75q

Supported benchmarks:

ec2-t3-xlarge-us-east-2: Supported benchmark langs: Python, R. Runs only benchmarks with cloud = True

test-mac-arm: Supported benchmark langs: C++, Python, R

ursa-i9-9960x: Supported benchmark langs: Python, R, JavaScript

ursa-thinkcentre-m75q: Supported benchmark langs: C++, Java
@cyb70289
cyb70289
deleted the

sve

branch
November 1, 2022 13:39
kou pushed a commit
that referenced
this pull request
Nov 15, 2022
@cyb70289@kou
ARROW-18162: [C++] Add Arm SVE compiler options (#14515)
f63804f
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with matched vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
Authored-by: Yibo Cai <yibo.cai@arm.com>
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
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, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Remove or un-stick sticky/fixed headers that block content\n(function() {\n function unstick() {\n document.querySelectorAll('header, nav, [role=\"banner\"], .header, .navbar, .sticky, .fixed-top, [style*=\"position: fixed\"], [style*=\"position:sticky\"]').forEach(function(el) {\n if (el.style.position === 'fixed' || el.style.position === 'sticky' || \n getComputedStyle(el).position === 'fixed' || getComputedStyle(el).position === 'sticky') {\n el.style.position = 'static';\n el.style.top = 'auto';\n el.style.zIndex = 'auto';\n }\n });\n }\n \n unstick();\n \n var observer = new MutationObserver(unstick);\n observer.observe(document.body, { childList: true, subtree: true, attributes: true, attributeFilter: ['style', 'class'] });\n})();", "Kill Sticky Headers");
}
} catch(__e) { console.warn('[Userscript:Kill Sticky Headers]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
ARROW-18162: [C++] Add Arm SVE compiler options - #14515
Merged
cyb70289 merged 2 commits into
apache:masterfrom 
cyb70289:sve
Nov 1, 2022
Merged
ARROW-18162: [C++] Add Arm SVE compiler options#14515
cyb70289 merged 2 commits into
apache:masterfrom 
cyb70289:sve
Conversation
@cyb70289
@cyb70289cyb70289
commented
Oct 26, 2022•

edited

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As xsimd only supports fixed-size SVE, we have to specify vector size

explicitly on command line. And the binary can only run on hardware

with matched vector size. Otherwise, the code behaviour is undefined.

E.g., cmake -DARROW_SIMD_LEVEL=SVE256 ..

According macro ARROW_HAVE_SVE256 and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size

agnostic SVE code without specifying the vector size.

E.g., cmake -DARROW_SIMD_LEVEL=SVE ..
This PR also removes some unused Arm64 arch options.
@github-actions
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Oct 26, 2022

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https://issues.apache.org/jira/browse/ARROW-18162
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⚠️ Ticket has not been started in JIRA, please click 'Start Progress'.
pitrou
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Comment threadcpp/cmake_modules/SetupCxxFlags.cmake
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
Yes. SVE may be better when longer vector size is beneficial, or to leverage operations (e.g, scatter/gather) not availble in NEON.
cyb70289
cyb70289
commented
Oct 27, 2022
View reviewed changes
Comment threaddev/tasks/conda-recipes/arrow-cpp/build-pyarrow.sh
Outdated

@cyb70289
ARROW-18162: [C++] Add Arm SVE compiler options
aa8ee3e
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with that vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
@cyb70289
Remove ARROW_ARMV8_ARCH cmake option
f99b57a
@cyb70289
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@github-actions crossbow submit conda-{linux,osx}-*
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Unable to match any tasks for `conda-{linux,osx}-*`
The Archery job run can be found at: https://github.com/apache/arrow/actions/runs/3360036059

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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-19dd1864f2
TaskStatus
conda-linux-gcc-py310-arm64Azure
conda-linux-gcc-py310-cpuAzure
conda-linux-gcc-py310-cudaAzure
conda-linux-gcc-py310-ppc64leAzure
conda-linux-gcc-py37-arm64Azure
conda-linux-gcc-py37-cpu-r40Azure
conda-linux-gcc-py37-cpu-r41Azure
conda-linux-gcc-py37-cudaAzure
conda-linux-gcc-py37-ppc64leAzure
conda-linux-gcc-py38-arm64Azure
conda-linux-gcc-py38-cpuAzure
conda-linux-gcc-py38-cudaAzure
conda-linux-gcc-py38-ppc64leAzure
conda-linux-gcc-py39-arm64Azure
conda-linux-gcc-py39-cpuAzure
conda-linux-gcc-py39-cudaAzure
conda-linux-gcc-py39-ppc64leAzure
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@github-actions crossbow submit conda-osx-*
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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-457a7b106d
TaskStatus
conda-osx-arm64-clang-py310Azure
conda-osx-arm64-clang-py37Azure
conda-osx-arm64-clang-py38Azure
conda-osx-arm64-clang-py39Azure
conda-osx-clang-py310Azure
conda-osx-clang-py37Azure
conda-osx-clang-py37-r40Azure
conda-osx-clang-py37-r41Azure
conda-osx-clang-py38Azure
conda-osx-clang-py39Azure
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conda-osx-clang-py310/py37 build error looks not related.
https://dev.azure.com/ursacomputing/crossbow/_build/results?buildId=38774&view=logs&j=cf796865-97b7-5cd1-be8e-6e00ce4fd8cf&t=88ee2fb8-46fd-5c68-fde3-1c8d31ba2a5f&l=3570
@cyb70289
cyb70289
requested review from
kou and pitrouNovember 1, 2022 01:45
kou
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+1 for changes
I re-ran failed jobs.
@cyb70289
cyb70289
merged commit 16fd7f3
into
apache:masterNov 1, 2022
@ursabot
ursabot
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Nov 1, 2022

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Benchmark runs are scheduled for baseline = 2a5c773 and contender = 16fd7f3. 16fd7f3 is a master commit associated with this PR. Results will be available as each benchmark for each run completes.

Conbench compare runs links:

[Finished ⬇️0.0% ⬆️0.0%] ec2-t3-xlarge-us-east-2

[Failed ⬇️0.0% ⬆️0.0%] test-mac-arm

[Finished ⬇️0.54% ⬆️0.0%] ursa-i9-9960x

[Finished ⬇️0.32% ⬆️0.18%] ursa-thinkcentre-m75q

Buildkite builds:

[Finished] 16fd7f3f ec2-t3-xlarge-us-east-2

[Failed] 16fd7f3f test-mac-arm

[Finished] 16fd7f3f ursa-i9-9960x

[Finished] 16fd7f3f ursa-thinkcentre-m75q

[Finished] 2a5c7736 ec2-t3-xlarge-us-east-2

[Failed] 2a5c7736 test-mac-arm

[Finished] 2a5c7736 ursa-i9-9960x

[Finished] 2a5c7736 ursa-thinkcentre-m75q

Supported benchmarks:

ec2-t3-xlarge-us-east-2: Supported benchmark langs: Python, R. Runs only benchmarks with cloud = True

test-mac-arm: Supported benchmark langs: C++, Python, R

ursa-i9-9960x: Supported benchmark langs: Python, R, JavaScript

ursa-thinkcentre-m75q: Supported benchmark langs: C++, Java
@cyb70289
cyb70289
deleted the

sve

branch
November 1, 2022 13:39
kou pushed a commit
that referenced
this pull request
Nov 15, 2022
@cyb70289@kou
ARROW-18162: [C++] Add Arm SVE compiler options (#14515)
f63804f
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with matched vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
Authored-by: Yibo Cai <yibo.cai@arm.com>
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
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, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Universal Dark Mode - works on any site\n(function() {\n var enabled = true;\n \n function applyDarkMode() {\n if (!enabled) return;\n \n // Create style element if it doesn't exist\n var style = document.getElementById('universal-dark-mode-style');\n if (!style) {\n style = document.createElement('style');\n style.id = 'universal-dark-mode-style';\n document.head.appendChild(style);\n }\n \n // Dark mode CSS - inverts colors but preserves images/video\n style.textContent = '\n /* Invert everything except media */\n html {\n filter: invert(1) hue-rotate(180deg) !important;\n background: #1a1a2e !important;\n }\n \n /* Restore images, videos, iframes, canvas */\n img, video, iframe, canvas, svg, picture, [style*=\"background-image\"] {\n filter: invert(1) hue-rotate(180deg) !important;\n }\n \n /* Preserve specific elements that should not be inverted */\n .no-dark-mode, .no-dark-mode *,\n [data-theme=\"light\"], [data-theme=\"light\"],\n .ace_editor, .ace_editor *,\n .CodeMirror, .CodeMirror *,\n .monaco-editor, .monaco-editor *,\n .markdown-body pre, .markdown-body pre *,\n .highlight, .highlight *,\n pre code, pre code * {\n filter: none !important;\n }\n \n /* Fix common UI elements */\n .modal, .popup, .dropdown-menu, .tooltip, .popover {\n filter: invert(1) hue-rotate(180deg) !important;\n background: #2d2d44 !important;\n border-color: #444 !important;\n }\n \n /* Scrollbars */\n ::-webkit-scrollbar { background: #1a1a2e !important; }\n ::-webkit-scrollbar-thumb { background: #444 !important; }\n ::-webkit-scrollbar-thumb:hover { background: #555 !important; }\n \n /* Selection */\n ::selection { background: #4ecdc4 !important; color: #1a1a2e !important; }\n ::-moz-selection { background: #4ecdc4 !important; color: #1a1a2e !important; }\n ';\n }\n \n function removeDarkMode() {\n var style = document.getElementById('universal-dark-mode-style');\n if (style) style.remove();\n }\n \n // Toggle with Alt+Shift+D\n document.addEventListener('keydown', function(e) {\n if (e.altKey && e.shiftKey && e.key === 'D') {\n e.preventDefault();\n enabled = !enabled;\n if (enabled) {\n applyDarkMode();\n console.log('[Universal Dark Mode] Enabled');\n } else {\n removeDarkMode();\n console.log('[Universal Dark Mode] Disabled');\n }\n }\n });\n \n // Apply on load\n applyDarkMode();\n \n // Re-apply on dynamic content\n var observer = new MutationObserver(function(mutations) {\n if (enabled && !document.getElementById('universal-dark-mode-style')) {\n applyDarkMode();\n }\n });\n observer.observe(document.head, { childList: true });\n \n console.log('[Universal Dark Mode] Loaded - Press Alt+Shift+D to toggle');\n})();", "Universal Dark Mode");
}
} catch(__e) { console.warn('[Userscript:Universal Dark Mode]', __e); }
})();
})();

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ARROW-18162: [C++] Add Arm SVE compiler options - #14515
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ARROW-18162: [C++] Add Arm SVE compiler options#14515
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Oct 26, 2022•

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As xsimd only supports fixed-size SVE, we have to specify vector size

explicitly on command line. And the binary can only run on hardware

with matched vector size. Otherwise, the code behaviour is undefined.

E.g., cmake -DARROW_SIMD_LEVEL=SVE256 ..

According macro ARROW_HAVE_SVE256 and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size

agnostic SVE code without specifying the vector size.

E.g., cmake -DARROW_SIMD_LEVEL=SVE ..
This PR also removes some unused Arm64 arch options.
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https://issues.apache.org/jira/browse/ARROW-18162
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⚠️ Ticket has not been started in JIRA, please click 'Start Progress'.
pitrou
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
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It seems we could also use SVE in src/arrow/util/bpacking.cc, src/arrow/util/utf8_internal.h, as well as src/arrow/csv/lexing_internal.h and src/arrow/csv/writer.cc?
Yes. SVE may be better when longer vector size is beneficial, or to leverage operations (e.g, scatter/gather) not availble in NEON.
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@cyb70289
ARROW-18162: [C++] Add Arm SVE compiler options
aa8ee3e
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with that vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
@cyb70289
Remove ARROW_ARMV8_ARCH cmake option
f99b57a
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@github-actions crossbow submit conda-{linux,osx}-*
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Unable to match any tasks for `conda-{linux,osx}-*`
The Archery job run can be found at: https://github.com/apache/arrow/actions/runs/3360036059

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@github-actions crossbow submit conda-linux-*
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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-19dd1864f2
TaskStatus
conda-linux-gcc-py310-arm64Azure
conda-linux-gcc-py310-cpuAzure
conda-linux-gcc-py310-cudaAzure
conda-linux-gcc-py310-ppc64leAzure
conda-linux-gcc-py37-arm64Azure
conda-linux-gcc-py37-cpu-r40Azure
conda-linux-gcc-py37-cpu-r41Azure
conda-linux-gcc-py37-cudaAzure
conda-linux-gcc-py37-ppc64leAzure
conda-linux-gcc-py38-arm64Azure
conda-linux-gcc-py38-cpuAzure
conda-linux-gcc-py38-cudaAzure
conda-linux-gcc-py38-ppc64leAzure
conda-linux-gcc-py39-arm64Azure
conda-linux-gcc-py39-cpuAzure
conda-linux-gcc-py39-cudaAzure
conda-linux-gcc-py39-ppc64leAzure
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@github-actions crossbow submit conda-osx-*
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Revision: f99b57a
Submitted crossbow builds: ursacomputing/crossbow @ actions-457a7b106d
TaskStatus
conda-osx-arm64-clang-py310Azure
conda-osx-arm64-clang-py37Azure
conda-osx-arm64-clang-py38Azure
conda-osx-arm64-clang-py39Azure
conda-osx-clang-py310Azure
conda-osx-clang-py37Azure
conda-osx-clang-py37-r40Azure
conda-osx-clang-py37-r41Azure
conda-osx-clang-py38Azure
conda-osx-clang-py39Azure
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conda-osx-clang-py310/py37 build error looks not related.
https://dev.azure.com/ursacomputing/crossbow/_build/results?buildId=38774&view=logs&j=cf796865-97b7-5cd1-be8e-6e00ce4fd8cf&t=88ee2fb8-46fd-5c68-fde3-1c8d31ba2a5f&l=3570
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kou and pitrouNovember 1, 2022 01:45
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+1 for changes
I re-ran failed jobs.
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apache:masterNov 1, 2022
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Benchmark runs are scheduled for baseline = 2a5c773 and contender = 16fd7f3. 16fd7f3 is a master commit associated with this PR. Results will be available as each benchmark for each run completes.

Conbench compare runs links:

[Finished ⬇️0.0% ⬆️0.0%] ec2-t3-xlarge-us-east-2

[Failed ⬇️0.0% ⬆️0.0%] test-mac-arm

[Finished ⬇️0.54% ⬆️0.0%] ursa-i9-9960x

[Finished ⬇️0.32% ⬆️0.18%] ursa-thinkcentre-m75q

Buildkite builds:

[Finished] 16fd7f3f ec2-t3-xlarge-us-east-2

[Failed] 16fd7f3f test-mac-arm

[Finished] 16fd7f3f ursa-i9-9960x

[Finished] 16fd7f3f ursa-thinkcentre-m75q

[Finished] 2a5c7736 ec2-t3-xlarge-us-east-2

[Failed] 2a5c7736 test-mac-arm

[Finished] 2a5c7736 ursa-i9-9960x

[Finished] 2a5c7736 ursa-thinkcentre-m75q

Supported benchmarks:

ec2-t3-xlarge-us-east-2: Supported benchmark langs: Python, R. Runs only benchmarks with cloud = True

test-mac-arm: Supported benchmark langs: C++, Python, R

ursa-i9-9960x: Supported benchmark langs: Python, R, JavaScript

ursa-thinkcentre-m75q: Supported benchmark langs: C++, Java
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November 1, 2022 13:39
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Nov 15, 2022
@cyb70289@kou
ARROW-18162: [C++] Add Arm SVE compiler options (#14515)
f63804f
As xsimd only supports fixed-size SVE, we have to specify vector size
explicitly on command line. And the binary can only run on hardware
with matched vector size. Otherwise, the code behaviour is undefined.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE256 ..`
According macro `ARROW_HAVE_SVE256` and cmake variable are defined.
We can also leverage compiler auto vectorization to generate size
agnostic SVE code without specifying the vector size.
E.g., `cmake -DARROW_SIMD_LEVEL=SVE ..`
This PR also removes some unused Arm64 arch options.
Authored-by: Yibo Cai <yibo.cai@arm.com>
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
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