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HVX scheduling and bench-marking of TE element-wise add - #10604

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csullivan merged 1 commit into
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cconvey:simple-hvx1
Apr 13, 2022
Merged

HVX scheduling and bench-marking of TE element-wise add#10604
csullivan merged 1 commit into
apache:mainfrom
cconvey:simple-hvx1

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@cconvey

@cconveycconvey commented Mar 14, 2022

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Thanks for contributing to TVM! Please refer to guideline https://tvm.apache.org/docs/contribute/ for useful information and tips. After the pull request is submitted, please request code reviews from Reviewers by @ them in the pull request thread.

@cconvey
cconveyforce-pushed the simple-hvx1 branch 2 times, most recently from 9116e50 to 3b1ad05CompareMarch 24, 2022 19:06
@cconvey

cconvey commented Mar 24, 2022•
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One thing the add_hvx test does is create a CSV file with the benchmark results. Here's an example of those results (pulled into Google Sheets for readability)
image

@cconvey

cconvey commented Mar 24, 2022•
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CC: @csullivan@mehrdadh@adstraw@Lunderberg@supersat@JosephTheOctonaut

@cconveycconvey changed the title [WIP] hvx scheduling of TE for element-wise addHVX scheduling and bench-marking of TE element-wise addMar 24, 2022
cconvey
cconvey commented Mar 24, 2022
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cconvey
cconvey commented Mar 24, 2022
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I like the functionality! The comments are mainly useful idioms and utilities in python/pytest that can help improve the readability.

Comment threadtests/python/contrib/test_hexagon/test_launcher.py Outdated
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Comment threadtests/python/contrib/test_hexagon/test_launcher.py Outdated
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cconvey
cconvey commented Mar 28, 2022
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@cconvey
cconveyforce-pushed the simple-hvx1 branch 5 times, most recently from f676426 to 8a74b7cCompareApril 1, 2022 16:43
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LGTM, just one small change I'd recommend to remove an unused variable.

Comment threadtests/python/contrib/test_hexagon/benchmark_hexagon.py Outdated
@cconvey
cconveyforce-pushed the simple-hvx1 branch 2 times, most recently from 1defba7 to a708594CompareApril 12, 2022 16:18
Christian Convey
[hexagon] 'add_hvx' test to explore HVX usage.
f2a1ca6
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
@cconvey
cconvey requested a review from LunderbergApril 12, 2022 17:35
Lunderberg
Lunderberg approved these changes Apr 13, 2022
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Thank you for making the changes, and the updated version looks good to me!

@csullivan
csullivan merged commit ce8f83e into apache:mainApr 13, 2022
@csullivan

csullivan commented Apr 13, 2022

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Thank you @cconvey and @Lunderberg for the great PR and fruitful discussion, this is merged!

masahi added a commit to masahi/tvm that referenced this pull request Apr 14, 2022
@masahi
Squashed commit of the following:
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Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
@cconvey
cconvey deleted the simple-hvx1 branch April 14, 2022 14:02
masahi added a commit to masahi/tvm that referenced this pull request Apr 14, 2022
@masahi
Squashed commit of the following:
434d29a
commit dcb628d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 17:10:27 2022 +0900
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add conv2d relay test
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add dense and bmm test
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conv2d topi test working
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share op strategy between cuda and rocm
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dp4a works
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Skip applying sch_rule when both ann and sch_rule are defined
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add DP4A intrin
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works
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try / catch in ThreadedApply
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allow missing schedule_rule in post order apply
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VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
masahi added a commit to masahi/tvm that referenced this pull request Apr 14, 2022
@masahi
Squashed commit of the following:
401b331
commit dcb628d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 17:10:27 2022 +0900
Squashed commit of the following:
commit dd956ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:53:34 2022 +0900
add conv2d relay test
commit 7291e47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:46:05 2022 +0900
add dense and bmm test
commit a957dde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:32:43 2022 +0900
conv2d topi test working
commit 6d53c50
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:33:38 2022 +0900
add mattr kind
commit 3761bd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:12:14 2022 +0900
update dot prod intrin
commit e781ee1
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:02:43 2022 +0900
black
commit b2208a7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:58:10 2022 +0900
cleanup
commit f8bc306
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:35:02 2022 +0900
[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
commit 0225f2b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:56:10 2022 +0900
share op strategy between cuda and rocm
commit 762c7e8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:28:34 2022 +0900
fixed rocm batch_matmul strategy for mixed i8i8i32
commit ce53e8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:17:30 2022 +0900
add rocm sdot4 TIR intrin
commit f4562b9
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:03:44 2022 +0900
rocm sdot4 works
commit 6cc6280
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 05:32:07 2022 +0900
more wip
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
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Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
masahi added a commit to masahi/tvm that referenced this pull request Apr 14, 2022
@masahi
Squashed commit of the following:
f499e60
commit dcb628d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 17:10:27 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:53:34 2022 +0900
add conv2d relay test
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:46:05 2022 +0900
add dense and bmm test
commit a957dde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:32:43 2022 +0900
conv2d topi test working
commit 6d53c50
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:33:38 2022 +0900
add mattr kind
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:12:14 2022 +0900
update dot prod intrin
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Date: Thu Apr 14 11:02:43 2022 +0900
black
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Date: Thu Apr 14 10:58:10 2022 +0900
cleanup
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:35:02 2022 +0900
[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:56:10 2022 +0900
share op strategy between cuda and rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
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fixed rocm batch_matmul strategy for mixed i8i8i32
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:17:30 2022 +0900
add rocm sdot4 TIR intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:03:44 2022 +0900
rocm sdot4 works
commit 6cc6280
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 05:32:07 2022 +0900
more wip
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
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Author: Masahiro Masuda <masahi129@gmail.com>
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Skip applying sch_rule when both ann and sch_rule are defined
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
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Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
AndrewZhaoLuo added a commit to AndrewZhaoLuo/tvm that referenced this pull request Apr 15, 2022
@AndrewZhaoLuo
Merge branch 'main' into aluo/fix-qlinearconv-grouped
ce8bec3
* main: (527 commits)
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
[COMMUNITY] @yzh119 -> Reviewer (apache#10993)
[Metaschedule] Make custom schedule_rule registration optional (apache#10975)
[ONNX] Add imports for BERT contrib operators (apache#10949)
sort axes (apache#10985)
[Hexagon] Remove HexagonBuffer external constructor and support (apache#10978)
[CI] Update GPU image (apache#10992)
[Runtime][Vulkan] Add RGP support to TVM for vulkan device (apache#10953)
[FIX] resolve int64/32 for AttrStmtNode (apache#10983)
[TVMC] Allow output module name to be passed as a command line argument (apache#10962)
[ONNX] Add MatMulInteger importer (apache#10450)
[COMMUNITY] @guberti -> Reviewer (apache#10976)
Support `qnn.conv2d` in FoldExplicitPading (apache#10982)
change Hexagon docker version (apache#10981)
remove exception handling of autotvm xgboost extract functions (apache#10948)
[CUDNN] Add partitioning support for conv2d and log_softmax (apache#10961)
[Hexagon][LLVM] Enable/test tensorized Hexagon DMA on 2d transformed layout (apache#10905)
[Hexagon] Move aot/graph_executor interactions into launcher (apache#10907)
[HEXAGON] Split huge 1D DMA Transfers into smaller transfers with legal sizes. (apache#10971)
[CI][DOCKER] Add pytest-lazy-fixture to images (apache#10970)
...
masahi added a commit to masahi/tvm that referenced this pull request Apr 15, 2022
@masahi
Squashed commit of the following:
90e7d89
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 15 04:11:02 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 17:10:27 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:53:34 2022 +0900
add conv2d relay test
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Author: Masahiro Masuda <masahi129@gmail.com>
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add dense and bmm test
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Author: Masahiro Masuda <masahi129@gmail.com>
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conv2d topi test working
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add mattr kind
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update dot prod intrin
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Date: Thu Apr 14 11:02:43 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:35:02 2022 +0900
[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:56:10 2022 +0900
share op strategy between cuda and rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:28:34 2022 +0900
fixed rocm batch_matmul strategy for mixed i8i8i32
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Author: Masahiro Masuda <masahi129@gmail.com>
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add rocm sdot4 TIR intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
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rocm sdot4 works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 05:32:07 2022 +0900
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Date: Thu Apr 14 03:47:37 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
masahi added a commit to masahi/tvm that referenced this pull request Apr 17, 2022
@masahi
Squashed commit of the following:
776c04b
commit f499e60
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 15 04:11:02 2022 +0900
Squashed commit of the following:
commit dcb628d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 17:10:27 2022 +0900
Squashed commit of the following:
commit dd956ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:53:34 2022 +0900
add conv2d relay test
commit 7291e47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:46:05 2022 +0900
add dense and bmm test
commit a957dde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:32:43 2022 +0900
conv2d topi test working
commit 6d53c50
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:33:38 2022 +0900
add mattr kind
commit 3761bd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:12:14 2022 +0900
update dot prod intrin
commit e781ee1
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:02:43 2022 +0900
black
commit b2208a7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:58:10 2022 +0900
cleanup
commit f8bc306
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:35:02 2022 +0900
[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
commit 0225f2b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:56:10 2022 +0900
share op strategy between cuda and rocm
commit 762c7e8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:28:34 2022 +0900
fixed rocm batch_matmul strategy for mixed i8i8i32
commit ce53e8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:17:30 2022 +0900
add rocm sdot4 TIR intrin
commit f4562b9
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:03:44 2022 +0900
rocm sdot4 works
commit 6cc6280
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 05:32:07 2022 +0900
more wip
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
masahi added a commit to masahi/tvm that referenced this pull request Apr 20, 2022
@masahi
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commit 928668b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 16 08:48:56 2022 +0900
Reworking GetTensorizeloopmapping
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 16 08:16:50 2022 +0900
fixed bad merge
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 15 04:11:02 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 17:10:27 2022 +0900
Squashed commit of the following:
commit dd956ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:53:34 2022 +0900
add conv2d relay test
commit 7291e47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:46:05 2022 +0900
add dense and bmm test
commit a957dde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:32:43 2022 +0900
conv2d topi test working
commit 6d53c50
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:33:38 2022 +0900
add mattr kind
commit 3761bd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:12:14 2022 +0900
update dot prod intrin
commit e781ee1
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:02:43 2022 +0900
black
commit b2208a7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:58:10 2022 +0900
cleanup
commit f8bc306
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:35:02 2022 +0900
[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
commit 0225f2b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:56:10 2022 +0900
share op strategy between cuda and rocm
commit 762c7e8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:28:34 2022 +0900
fixed rocm batch_matmul strategy for mixed i8i8i32
commit ce53e8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:17:30 2022 +0900
add rocm sdot4 TIR intrin
commit f4562b9
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:03:44 2022 +0900
rocm sdot4 works
commit 6cc6280
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 05:32:07 2022 +0900
more wip
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
masahi added a commit to masahi/tvm that referenced this pull request Apr 20, 2022
@masahi
Squashed commit of the following:
7275684
commit 3eba93a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 20 12:37:27 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 16 08:48:56 2022 +0900
Reworking GetTensorizeloopmapping
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
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Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
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Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 17:10:27 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:53:34 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:46:05 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:32:43 2022 +0900
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black
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Author: Masahiro Masuda <masahi129@gmail.com>
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[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:56:10 2022 +0900
share op strategy between cuda and rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:28:34 2022 +0900
fixed rocm batch_matmul strategy for mixed i8i8i32
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Author: Masahiro Masuda <masahi129@gmail.com>
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add rocm sdot4 TIR intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:03:44 2022 +0900
rocm sdot4 works
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Author: Masahiro Masuda <masahi129@gmail.com>
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[WIP] adding DP4A support to rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
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Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
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Author: Masahiro Masuda <masahi129@gmail.com>
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dp4a works
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Skip applying sch_rule when both ann and sch_rule are defined
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fixed intrin description
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
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Author: Masahiro Masuda <masahi129@gmail.com>
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revert change in task_scheduler.cc
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
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try graceful exit in parallel_for_dynamic
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
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Date: Thu Apr 7 16:57:14 2022 +0900
compiled
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
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black
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pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
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simplify import
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Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
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Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
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Date: Thu Apr 7 05:41:13 2022 +0900
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vectorized init loop
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Author: Masahiro Masuda <masahi129@gmail.com>
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tensorize worked
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Author: Masahiro Masuda <masahi129@gmail.com>
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TilingwithTensorIntrin works
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Author: Masahiro Masuda <masahi129@gmail.com>
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black
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pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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use vectorlow/high in arm intrin
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Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
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Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
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Date: Thu Apr 7 08:17:43 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
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[WIP] adding DP4A support to rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
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commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
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Author: Masahiro Masuda <masahi129@gmail.com>
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wrap tensorize with try/catch
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
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Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
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Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
masahi added a commit to masahi/tvm that referenced this pull request Apr 21, 2022
@masahi
Squashed commit of the following:
7e9ffab
commit e8c4405
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 20 16:52:02 2022 +0900
cpplint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 20 16:49:36 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
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Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 16 08:48:56 2022 +0900
Reworking GetTensorizeloopmapping
commit a80e639
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 16 08:16:50 2022 +0900
fixed bad merge
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 15 19:46:44 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 15 04:11:02 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 17:10:27 2022 +0900
Squashed commit of the following:
commit dd956ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:53:34 2022 +0900
add conv2d relay test
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:46:05 2022 +0900
add dense and bmm test
commit a957dde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:32:43 2022 +0900
conv2d topi test working
commit 6d53c50
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:33:38 2022 +0900
add mattr kind
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:12:14 2022 +0900
update dot prod intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:02:43 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:58:10 2022 +0900
cleanup
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:35:02 2022 +0900
[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
commit 0225f2b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:56:10 2022 +0900
share op strategy between cuda and rocm
commit 762c7e8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:28:34 2022 +0900
fixed rocm batch_matmul strategy for mixed i8i8i32
commit ce53e8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:17:30 2022 +0900
add rocm sdot4 TIR intrin
commit f4562b9
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:03:44 2022 +0900
rocm sdot4 works
commit 6cc6280
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 05:32:07 2022 +0900
more wip
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
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Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit 88cbe5e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 20 16:44:54 2022 +0900
add doc
commit e8155a5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 20 16:25:24 2022 +0900
add tests
commit 70ac9c1
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 20 12:47:45 2022 +0900
[Metaschedule] Add TilingwithTensorIntrin
altanh pushed a commit to altanh/tvm that referenced this pull request Apr 28, 2022
Christian Convey@altanh
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
0d762b3
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
@driazatidriazati mentioned this pull request Jul 14, 2022
Closed
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@cconvey@csullivan@Lunderberg