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[Hexagon] Less aggressive adb state clean up - #10909

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mehrdadh merged 3 commits into
apache:mainfrom
csullivan:hexagon_port_forwarding
Apr 13, 2022
Merged

[Hexagon] Less aggressive adb state clean up#10909
mehrdadh merged 3 commits into
apache:mainfrom
csullivan:hexagon_port_forwarding

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@csullivan

@csullivancsullivan commented Apr 5, 2022

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Changes:

  • Issue SIGINT before SIGKILL to allow the server time to clean up and unbind the port on Android
  • Only remove forward (and reversed) ports set during a given session rather than globally applying remove all.

@csullivan
csullivan requested a review from mehrdadhApril 5, 2022 21:55
@csullivan

csullivan commented Apr 5, 2022

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cc @mehrdadh@Lunderberg this one was an attempt to stabilize the adb issues we've seen. I'm not sure I see much improvement, but would like your feedback. Thanks

Lunderberg
Lunderberg approved these changes Apr 6, 2022
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LGTM. There's a couple of questions and musing on edge cases, but I think changes as-is are an improvement over the existing behavior, so we can have them in follow-up PRs if necessary.

Comment threadpython/tvm/contrib/hexagon/build.py Outdated
Comment threadpython/tvm/contrib/hexagon/build.py
"""Setup the ADB connection and execute the server script."""

# Removed pre-defined forward/reverse rules
subprocess.check_call(self._adb_device_sub_cmd + ["forward", "--remove-all"])

@LunderbergLunderbergApr 6, 2022

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Do we want to clean up port forwards that have been opened for more than N days? The .stop_server() method may not be called if a segfault occurs, and that may leave ports open unnecessarily.

Comment threadpython/tvm/contrib/hexagon/build.py Outdated
subprocess.check_call(
self._adb_device_sub_cmd
+ ["forward", f"tcp:{rpc_server_port+i}", f"tcp:{rpc_server_port+i}"]
self._adb_device_sub_cmd + ["forward", f"tcp:{port}", f"tcp:{port}"]

@LunderbergLunderbergApr 6, 2022

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If a port forward already exists, does adb exit with a non-zero return code? If the adb call exits with a zero return code in that case, then there are two processes trying to start port forwards on overlapping ranges would result in double clean-up occurring.

@LunderbergLunderbergApr 6, 2022

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Also, I think we should move the self.forwarded_ports_.append(port) to be after the subprocess call. That way, a cleanup that occurs as the stack unwinds (e.g. the hexagon_launcher fixture) wouldn't try to clean up the failed port forward.

@csullivancsullivanApr 12, 2022•
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Thank you for the thought on this, and no adb doesn't complain about multiple attempts to forward the same port. I decided to be more rigorous with port checking and only forward ports that are not already forwarded by adb or bound by another process. This seems to have greatly improved the stability. PTAL at ed610c4.

Comment threadpython/tvm/contrib/hexagon/build.py Outdated
# Wait for processes to destruct cleanly after receiving the intrupt
subprocess.Popen(self._adb_device_sub_cmd + ["shell", "sleep", "0.1s"])
# Kill process children
self._adb_device_sub_cmd + ["shell", f"pkill -P `cat {self._workspace}/rpc_pid.txt`"]

@LunderbergLunderbergApr 6, 2022

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I wonder if we could set the process group for the subprocesses launched by PopenWorker. Those are the ones that tend to be left-over. The pkill -P command would send signals to the direct children of the main process, but not to any grandchildren (e.g. main process starts a worker subprocess, which starts a compilation subprocess), or to any processes started after the child process is killed but before the parent process is killed (e.g. main process interprets the closing child as a failed test case, starts a new test case). It looks like it would be relatively straightfoward to have Popen calls started as the same process group, so that they would all receive the signal simultaneously.

@csullivan
Only remove port forwarding applied in a session
9b6cec4
to avoid affecting global adb state.
@csullivan
Send SIGINT to attempt to allow remote
8782d48
server to cleanup and undbind port in
deconstruction
@csullivan
Only attempt to forward ports not in use by
ed610c4
adb or the system.
Lunderberg
Lunderberg approved these changes Apr 13, 2022
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LGTM, just a few general nitpicks that could be handled either here or in a follow-up.

Comment threadpython/tvm/contrib/hexagon/build.py
for item in self.ANDROID_HEXAGON_RPC_FILES:
self._copy_to_remote(lib_dir / item, self._workspace / item)

def _process_forwarded_ports(self):

@LunderbergLunderbergApr 13, 2022

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Nit: Rename to _existing_forwarded_ports or _get_forwarded_ports. The current name reads as if this is performing some processing on each forwarded port.

Comment threadpython/tvm/contrib/hexagon/build.py
# Enable port forward for RPC server. We forward the first ten open ports
# starting from the rpc_server_port
port = rpc_server_port
while len(self.forwarded_ports_) < 10:

@LunderbergLunderbergApr 13, 2022

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I believe the total number of ports isn't important, instead trying to match the port range that may be attempted a server, when it searches for an available port to listen on. How often is the port already forwarded or in use, and would be be better to throw an error in those cases?

@csullivancsullivanApr 13, 2022

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Not sure throwing an error in these cases makes sense given that the user only cares about the functionality of their tests on hardware and doesn't want to see test failures based on bad port configurations.

If we change the RPC server to fail rather than search for a new port as it does now, then we can revisit the launcher code and have it try until successfully binding to a single port and remove the port range nonsense.

@LunderbergLunderbergApr 13, 2022

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Good point, and that would make a lot of sense to me. I like the semantics of "bind here or error" much more than "bind here or maybe somewhere else or error". That makes sense for it to be a later change, and not something needed at the moment.

Comment threadpython/tvm/contrib/hexagon/build.py
)

self._reverse_ports(rpc_tracker_port)
self._forward_ports(rpc_server_port, existing_forwards)

@LunderbergLunderbergApr 13, 2022

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Nit: Since existing_forwards isn't used elsewhere, may be cleaner to generated it inside _forward_ports.

mehrdadh
mehrdadh approved these changes Apr 13, 2022
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LGTM, thanks for fixing this!

@mehrdadh
mehrdadh merged commit e370ed4 into apache:mainApr 13, 2022
masahi added a commit to masahi/tvm that referenced this pull request Apr 14, 2022
@masahi
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Author: Chris Sullivan <csullivan@octoml.ai>
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[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
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Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
masahi added a commit to masahi/tvm that referenced this pull request Apr 14, 2022
@masahi
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Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
masahi added a commit to masahi/tvm that referenced this pull request Apr 14, 2022
@masahi
Squashed commit of the following:
401b331
commit dcb628d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 17:10:27 2022 +0900
Squashed commit of the following:
commit dd956ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:53:34 2022 +0900
add conv2d relay test
commit 7291e47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:46:05 2022 +0900
add dense and bmm test
commit a957dde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:32:43 2022 +0900
conv2d topi test working
commit 6d53c50
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:33:38 2022 +0900
add mattr kind
commit 3761bd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:12:14 2022 +0900
update dot prod intrin
commit e781ee1
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:02:43 2022 +0900
black
commit b2208a7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:58:10 2022 +0900
cleanup
commit f8bc306
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:35:02 2022 +0900
[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
commit 0225f2b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:56:10 2022 +0900
share op strategy between cuda and rocm
commit 762c7e8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:28:34 2022 +0900
fixed rocm batch_matmul strategy for mixed i8i8i32
commit ce53e8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:17:30 2022 +0900
add rocm sdot4 TIR intrin
commit f4562b9
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:03:44 2022 +0900
rocm sdot4 works
commit 6cc6280
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 05:32:07 2022 +0900
more wip
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
masahi added a commit to masahi/tvm that referenced this pull request Apr 14, 2022
@masahi
Squashed commit of the following:
f499e60
commit dcb628d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 17:10:27 2022 +0900
Squashed commit of the following:
commit dd956ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:53:34 2022 +0900
add conv2d relay test
commit 7291e47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:46:05 2022 +0900
add dense and bmm test
commit a957dde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:32:43 2022 +0900
conv2d topi test working
commit 6d53c50
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:33:38 2022 +0900
add mattr kind
commit 3761bd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:12:14 2022 +0900
update dot prod intrin
commit e781ee1
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:02:43 2022 +0900
black
commit b2208a7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:58:10 2022 +0900
cleanup
commit f8bc306
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:35:02 2022 +0900
[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
commit 0225f2b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:56:10 2022 +0900
share op strategy between cuda and rocm
commit 762c7e8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:28:34 2022 +0900
fixed rocm batch_matmul strategy for mixed i8i8i32
commit ce53e8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:17:30 2022 +0900
add rocm sdot4 TIR intrin
commit f4562b9
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:03:44 2022 +0900
rocm sdot4 works
commit 6cc6280
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 05:32:07 2022 +0900
more wip
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
masahi added a commit to masahi/tvm that referenced this pull request Apr 15, 2022
@masahi
Squashed commit of the following:
90e7d89
commit f499e60
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 15 04:11:02 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 17:10:27 2022 +0900
Squashed commit of the following:
commit dd956ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:53:34 2022 +0900
add conv2d relay test
commit 7291e47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:46:05 2022 +0900
add dense and bmm test
commit a957dde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:32:43 2022 +0900
conv2d topi test working
commit 6d53c50
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:33:38 2022 +0900
add mattr kind
commit 3761bd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:12:14 2022 +0900
update dot prod intrin
commit e781ee1
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:02:43 2022 +0900
black
commit b2208a7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:58:10 2022 +0900
cleanup
commit f8bc306
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:35:02 2022 +0900
[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
commit 0225f2b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:56:10 2022 +0900
share op strategy between cuda and rocm
commit 762c7e8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:28:34 2022 +0900
fixed rocm batch_matmul strategy for mixed i8i8i32
commit ce53e8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:17:30 2022 +0900
add rocm sdot4 TIR intrin
commit f4562b9
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:03:44 2022 +0900
rocm sdot4 works
commit 6cc6280
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 05:32:07 2022 +0900
more wip
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
commit 2632899
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
masahi added a commit to masahi/tvm that referenced this pull request Apr 17, 2022
@masahi
Squashed commit of the following:
776c04b
commit f499e60
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 15 04:11:02 2022 +0900
Squashed commit of the following:
commit dcb628d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 17:10:27 2022 +0900
Squashed commit of the following:
commit dd956ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:53:34 2022 +0900
add conv2d relay test
commit 7291e47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:46:05 2022 +0900
add dense and bmm test
commit a957dde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:32:43 2022 +0900
conv2d topi test working
commit 6d53c50
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:33:38 2022 +0900
add mattr kind
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:12:14 2022 +0900
update dot prod intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 11:02:43 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:58:10 2022 +0900
cleanup
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:35:02 2022 +0900
[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
commit 0225f2b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:56:10 2022 +0900
share op strategy between cuda and rocm
commit 762c7e8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:28:34 2022 +0900
fixed rocm batch_matmul strategy for mixed i8i8i32
commit ce53e8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:17:30 2022 +0900
add rocm sdot4 TIR intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:03:44 2022 +0900
rocm sdot4 works
commit 6cc6280
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 05:32:07 2022 +0900
more wip
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
commit 0602f4a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
Squashed commit of the following:
commit 65b8bcf
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
commit 4f8f308
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
commit 1711be3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
commit 8a48fb5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
commit 4915c6a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
commit 7b3d71c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
commit 7666cd7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
commit db34397
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
commit 9e4f9df
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
commit 9d6741c
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
commit d8b2aa3
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
commit eb05d25
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
commit 5e6b0a0
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
commit 2b8c430
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
commit 7c21a9f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 07bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 15e60b4
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
masahi added a commit to masahi/tvm that referenced this pull request Apr 20, 2022
@masahi
Squashed commit of the following:
3eba93a
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 16 08:48:56 2022 +0900
Reworking GetTensorizeloopmapping
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Author: Masahiro Masuda <masahi129@gmail.com>
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Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
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Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
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[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
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share op strategy between cuda and rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
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rocm sdot4 works
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[WIP] adding DP4A support to rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
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Revert "Skip applying sch_rule when both ann and sch_rule are defined"
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
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Author: Masahiro Masuda <masahi129@gmail.com>
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dp4a works
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Skip applying sch_rule when both ann and sch_rule are defined
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Author: Masahiro Masuda <masahi129@gmail.com>
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add DP4A intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
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Author: Masahiro Masuda <masahi129@gmail.com>
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more hack to tensorize loop mapping to make resnet50 e2e work
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Author: Masahiro Masuda <masahi129@gmail.com>
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wip support pad + qnn.conv2d folding
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hack to tensorize loop mapping to make conv2d work
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revert change in task_scheduler.cc
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
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Author: Masahiro Masuda <masahi129@gmail.com>
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try graceful exit in parallel_for_dynamic
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
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Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
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Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
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clean up headers
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Date: Thu Apr 7 16:57:14 2022 +0900
compiled
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function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
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update vnni intrin name
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Merge: e0c5eb807bbb38
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Date: Thu Apr 7 11:44:47 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
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black
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pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
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Author: Masahiro Masuda <masahi129@gmail.com>
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Add ARM intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
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Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
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vectorized init loop
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tensorize worked
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simplify import
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use vectorlow/high in arm intrin
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Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
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Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
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Author: Masahiro Masuda <masahi129@gmail.com>
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add VNNI unittest
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
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Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
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HVX units.
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[WIP] adding DP4A support to rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
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Revert "Skip applying sch_rule when both ann and sch_rule are defined"
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
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Skip applying sch_rule when both ann and sch_rule are defined
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
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Date: Tue Apr 12 19:03:44 2022 +0900
works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
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Author: Masahiro Masuda <masahi129@gmail.com>
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wip support pad + qnn.conv2d folding
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Author: Masahiro Masuda <masahi129@gmail.com>
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hack to tensorize loop mapping to make conv2d work
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wrap tensorize with try/catch
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revert change in task_scheduler.cc
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
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filter out invalid candidate
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Author: Masahiro Masuda <masahi129@gmail.com>
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try graceful exit in parallel_for_dynamic
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[QNN] Fix broadcast for invalid axis
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
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Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
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Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
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Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
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Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
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Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
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Merge: e0c5eb807bbb38
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Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
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Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
masahi added a commit to masahi/tvm that referenced this pull request Apr 20, 2022
@masahi
Squashed commit of the following:
7275684
commit 3eba93a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 20 12:37:27 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 16 08:48:56 2022 +0900
Reworking GetTensorizeloopmapping
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 16 08:16:50 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
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Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 17:10:27 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:53:34 2022 +0900
add conv2d relay test
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:46:05 2022 +0900
add dense and bmm test
commit a957dde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 16:32:43 2022 +0900
conv2d topi test working
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
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update dot prod intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
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black
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 10:35:02 2022 +0900
[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
commit 0225f2b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:56:10 2022 +0900
share op strategy between cuda and rocm
commit 762c7e8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 08:28:34 2022 +0900
fixed rocm batch_matmul strategy for mixed i8i8i32
commit ce53e8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:17:30 2022 +0900
add rocm sdot4 TIR intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 06:03:44 2022 +0900
rocm sdot4 works
commit 6cc6280
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 05:32:07 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
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Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
commit 7086bdb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
commit 2409674
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
commit 613cb7e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
commit d4b496d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
commit 476129b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
commit 6ccde09
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
commit 2ce2066
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
commit 3a69353
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
commit 43e0b2f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
commit 823797e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
commit 4284a47
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
commit b87ef32
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
commit 2fc118b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
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refactored init
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
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Author: Masahiro Masuda <masahi129@gmail.com>
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remove log
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
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Author: Masahiro Masuda <masahi129@gmail.com>
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vectorized init loop
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 14 03:47:37 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 20:36:49 2022 +0900
[WIP] adding DP4A support to rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 14:03:25 2022 +0900
Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
fixed condition for real
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 09:57:42 2022 +0900
Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
commit daea033
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
commit eb0cae2
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 12:04:08 2022 +0900
hack to tensorize loop mapping to make conv2d work
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:34:13 2022 +0900
wrap tensorize with try/catch
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sun Apr 10 11:33:39 2022 +0900
revert change in task_scheduler.cc
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
commit d8226ff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 17:17:59 2022 +0900
filter out invalid candidate
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 10:09:48 2022 +0900
try graceful exit in parallel_for_dynamic
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Fri Apr 8 09:35:51 2022 +0900
[QNN] Fix broadcast for invalid axis
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
move TilingwithTensorIntrin to auto_tensorize.cc
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:28:45 2022 +0900
clean up headers
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:03:05 2022 +0900
refactored init
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
wip MultiLevelTiling refactor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
commit 40f9742
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
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Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
masahi added a commit to masahi/tvm that referenced this pull request Apr 21, 2022
@masahi
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Reworking GetTensorizeloopmapping
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Squashed commit of the following:
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
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[ROCM] Support dp4a on AMDGPU by sdot4 intrinsic
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Author: Masahiro Masuda <masahi129@gmail.com>
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share op strategy between cuda and rocm
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Author: Masahiro Masuda <masahi129@gmail.com>
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rocm sdot4 works
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[WIP] adding DP4A support to rocm
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Revert "Skip applying sch_rule when both ann and sch_rule are defined"
This reverts commit 4915c6a.
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
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Author: Masahiro Masuda <masahi129@gmail.com>
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dp4a works
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Author: Masahiro Masuda <masahi129@gmail.com>
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Skip applying sch_rule when both ann and sch_rule are defined
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
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Author: Masahiro Masuda <masahi129@gmail.com>
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add DP4A intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
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Author: Masahiro Masuda <masahi129@gmail.com>
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wip support pad + qnn.conv2d folding
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Author: Masahiro Masuda <masahi129@gmail.com>
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hack to tensorize loop mapping to make conv2d work
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wrap tensorize with try/catch
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Author: Masahiro Masuda <masahi129@gmail.com>
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revert change in task_scheduler.cc
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
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Author: Masahiro Masuda <masahi129@gmail.com>
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filter out invalid candidate
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Author: Masahiro Masuda <masahi129@gmail.com>
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try graceful exit in parallel_for_dynamic
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Author: Masahiro Masuda <masahi129@gmail.com>
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[QNN] Fix broadcast for invalid axis
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:51:15 2022 +0900
refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
rewrite_vnni -> rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:12:12 2022 +0900
VNNI -> WithIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:34:04 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 16:57:14 2022 +0900
compiled
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 12:51:55 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:58:33 2022 +0900
function doc string not supported by tvmscript
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Author: Masahiro Masuda <masahi129@gmail.com>
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update vnni intrin name
commit 4814f82
Merge: e0c5eb807bbb38
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
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Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
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Author: Masahiro Masuda <masahi129@gmail.com>
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refactored RewriteVNNI a bit
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
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Author: Masahiro Masuda <masahi129@gmail.com>
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Ported auto-tensorization code
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
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Date: Thu Apr 7 11:12:54 2022 +0900
pylint
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
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Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e370ed4
Author: Chris Sullivan <csullivan@octoml.ai>
Date: Wed Apr 13 15:19:41 2022 -0700
[Hexagon] Less aggressive adb state clean up (apache#10909)
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
commit ce8f83e
Author: Christian Convey <cconvey@octoml.ai>
Date: Wed Apr 13 16:25:39 2022 -0400
[hexagon] 'add_hvx' test to explore HVX usage. (apache#10604)
Add a unit test named 'add_hvx' to explore how various
scheduling choices, tensor sizes, etc. impact efficient usage of Hexagon
HVX units.
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Date: Thu Apr 14 03:47:37 2022 +0900
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 13:11:40 2022 +0900
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Revert "Skip applying sch_rule when both ann and sch_rule are defined"
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 09:31:05 2022 +0900
[Metaschedule] Support rocm and spirv
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 07:25:04 2022 +0900
dp4a works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 06:13:45 2022 +0900
Skip applying sch_rule when both ann and sch_rule are defined
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 13 04:40:31 2022 +0900
fixed intrin description
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:59:47 2022 +0900
add DP4A intrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 19:03:44 2022 +0900
works
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Tue Apr 12 12:49:52 2022 +0900
more hack to tensorize loop mapping to make resnet50 e2e work
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Mon Apr 11 13:40:59 2022 +0900
wip support pad + qnn.conv2d folding
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Author: Masahiro Masuda <masahi129@gmail.com>
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hack to tensorize loop mapping to make conv2d work
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Author: Masahiro Masuda <masahi129@gmail.com>
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wrap tensorize with try/catch
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Author: Masahiro Masuda <masahi129@gmail.com>
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revert change in task_scheduler.cc
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Sat Apr 9 05:54:10 2022 +0900
try / catch in ThreadedApply
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filter out invalid candidate
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try graceful exit in parallel_for_dynamic
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[QNN] Fix broadcast for invalid axis
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refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 20:48:17 2022 +0900
allow missing schedule_rule in post order apply
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 19:42:48 2022 +0900
refactor rewrite_tensorize
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 18:25:14 2022 +0900
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VNNI -> WithIntrin
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:45:41 2022 +0900
introduce TileForIntrin
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Date: Thu Apr 7 17:34:04 2022 +0900
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clean up headers
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 17:09:32 2022 +0900
clean up using namespace
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Author: Masahiro Masuda <masahi129@gmail.com>
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refactored init
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compiled
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wip MultiLevelTiling refactor
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Author: Masahiro Masuda <masahi129@gmail.com>
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function doc string not supported by tvmscript
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Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:56:45 2022 +0900
update vnni intrin name
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Date: Thu Apr 7 11:44:47 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
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Author: Masahiro Masuda <masahi129@gmail.com>
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Author: Masahiro Masuda <masahi129@gmail.com>
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black
commit 7a757fe
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 9a3e508
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit d8e43ec
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 625cd27
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 69e72b6
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 1351fde
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0ced85f
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit 38a5aca
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 88b763e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 711a007
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit e0c5eb8
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:42:26 2022 +0900
merge fix
commit b171748
Merge: 71fe3bd82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:33:59 2022 +0900
Merge branch 'tir-tensor-intrin' into auto-tensorize-vnni
commit 71fe3bd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:57:38 2022 +0900
move tensor intrin under tir
commit 0c51bad
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:12:39 2022 +0900
remove log
commit fed910e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:11:22 2022 +0900
more revert
commit 7150aff
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:44 2022 +0900
revert stmt_functor change
commit 155107b
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 06:10:09 2022 +0900
refactored RewriteVNNI a bit
commit ca15255
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:41:13 2022 +0900
add RewriteVNNI
commit dc9f71d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 05:38:56 2022 +0900
vectorized init loop
commit fcc31ee
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 04:55:36 2022 +0900
tensorize worked
commit 2b53437
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 19:11:05 2022 +0900
TilingwithTensorIntrin works
commit 86baa31
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 6 08:58:27 2022 +0900
Ported auto-tensorization code
commit 82e152a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:24:56 2022 +0900
more lint fix
commit 88d9bdd
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:16:08 2022 +0900
black
commit 31fe7eb
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 11:12:54 2022 +0900
pylint
commit 7876754
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:58:52 2022 +0900
simplify import
commit 56f2e9a
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:52:50 2022 +0900
use vectorlow/high in arm intrin
commit 995cc8d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:34:57 2022 +0900
fixed offset factor
commit 86bbd49
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 10:12:02 2022 +0900
Add ARM intrin
commit 120fd96
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:27:27 2022 +0900
use buffer syntax sugar
commit 0f0682d
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 08:17:43 2022 +0900
rename vnni.py to x86.py
commit f88c31e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:24:44 2022 +0900
add VNNI unittest
commit 6cc8009
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:10:06 2022 +0900
refactored existing test using VNNI intrin
commit 11a29c7
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Thu Apr 7 07:04:58 2022 +0900
[TIR] Add VNNI dot product intrinsic for TIR
commit 88cbe5e
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 20 16:44:54 2022 +0900
add doc
commit e8155a5
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 20 16:25:24 2022 +0900
add tests
commit 70ac9c1
Author: Masahiro Masuda <masahi129@gmail.com>
Date: Wed Apr 20 12:47:45 2022 +0900
[Metaschedule] Add TilingwithTensorIntrin
altanh pushed a commit to altanh/tvm that referenced this pull request Apr 28, 2022
@csullivan@altanh
[Hexagon] Less aggressive adb state clean up (apache#10909)
a1ff8c9
* Only remove port forwarding applied in a session
to avoid affecting global adb state.
* Send SIGINT to attempt to allow remote
server to cleanup and undbind port in
deconstruction
* Only attempt to forward ports not in use by
adb or the system.
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@LunderbergLunderbergLunderberg approved these changes
@mehrdadhmehrdadhmehrdadh approved these changes

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@csullivan@Lunderberg@mehrdadh