[Fuzzlyn] x86 test failure involving field and division

[tannergooding]

https://dev.azure.com/dnceng-public/public/_build/results?buildId=196071&view=ms.vss-build-web.run-extensions-tab

// Generated by Fuzzlyn v1.5 on 2023-03-07 17:55:15
// Run on X86 Windows
// Seed: 7526964204781879473
// Reduced from 425.4 KiB to 0.4 KiB in 00:12:20
// Debug: Prints 0 line(s)
// Release: Prints 1 line(s)
public struct S0
{
 public ulong F1;
}

public class C0
{
 public uint F0;
}

public class C1
{
 public S0 F1;
}

public class Program
{
 public static C0 s_10 = new C0();
 public static C1 s_64 = new C1();
 public static void Main()
 {
 if (0 > (int)(s_10.F0 / 2699312582U))
 {
 var vr5 = s_64.F1.F1;
 System.Console.WriteLine(vr5);
 }
 }
}

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Issue Details

---

https://dev.azure.com/dnceng-public/public/_build/results?buildId=196071&view=ms.vss-build-web.run-extensions-tab

// Generated by Fuzzlyn v1.5 on 2023-03-07 17:55:15
// Run on X86 Windows
// Seed: 7526964204781879473
// Reduced from 425.4 KiB to 0.4 KiB in 00:12:20
// Debug: Prints 0 line(s)
// Release: Prints 1 line(s)
public struct S0
{
 public ulong F1;
}

public class C0
{
 public uint F0;
}

public class C1
{
 public S0 F1;
}

public class Program
{
 public static C0 s_10 = new C0();
 public static C1 s_64 = new C1();
 public static void Main()
 {
 if (0 > (int)(s_10.F0 / 2699312582U))
 {
 var vr5 = s_64.F1.F1;
 System.Console.WriteLine(vr5);
 }
 }
}

Author:	tannergooding
Assignees:	-
Labels:	area-CodeGen-coreclr
Milestone:	-

[EgorBo]

cc @TIHan can this be caused by #82733?

[jakobbotsch]

From a bisection this is from 8a28b11

[jakobbotsch]

We transform

N013 ( 32, 38) [000008] -c-XG------ t8 = ▌ IND int <l:$2c3, c:$2c4>
N014 ( 1, 4) [000009] -c-----N--- t9 = CNS_INT int -0x5f1bc23a $42
 ┌──▌ t8 int 
 ├──▌ t9 int 
N015 ( 53, 45) [000010] N--XG----U- t10 = ▌ GE int 
N016 ( 1, 1) [000000] -c--------- t0 = CNS_INT int 0 $44
 ┌──▌ t10 int 
 ├──▌ t0 int 
N017 ( 55, 47) [000011] ---XG--N--- ▌ CMP void 
N018 ( 57, 49) [000012] ---XG------ JCC void cond=SGE <l:$149, c:$148>

to

N013 ( 32, 38) [000008] -c-XG------ t8 = ▌ IND int <l:$2c3, c:$2c4>
N014 ( 1, 4) [000009] -c-----N--- t9 = CNS_INT int -0x5f1bc23a $42
 ┌──▌ t8 int 
 ├──▌ t9 int 
N015 ( 53, 45) [000010] ---XG----U- ▌ CMP void 
N018 ( 57, 49) [000012] ---XG------ JCC void cond=UGE

Looks like we mess up the sign of the condition at some point.

[jakobbotsch]

Another issue in that new optimization:

// Generated by Fuzzlyn v1.5 on 2023-03-08 14:45:20
// Run on Arm64 MacOS
// Seed: 4799288502595168691
// Reduced from 173.8 KiB to 0.3 KiB in 00:00:42
// Hits JIT assert in Release:
// Assertion failed 'genTypeSize(op1Type) == genTypeSize(op2Type)' in 'Program:Main(Fuzzlyn.ExecutionServer.IRuntime)' during 'Generate code' (IL size 76; hash 0xade6b36b; FullOpts)
// 
// File: /Users/runner/work/1/s/src/coreclr/jit/codegenarm64.cpp Line: 4521
// 
public class C0
{
 public long F0;
 public uint F1;
 public sbyte F2;
}

public class Program
{
 public static C0 s_3;
 public static void Main()
 {
 if ((s_3.F0 < s_3.F2) & ((s_3.F1 / 13548999118840769392UL) <= 0))
 {
 bool vr1 = 0 != s_3.F0++;
 }
 }
}

The optimization needs to take into account that the EQ/NE may essentially function as a cast:

N024 ( 5, 6) [000011] ----GO---U- t11 = ▌ CAST long <- ulong <- uint <l:$248, c:$24a>
N025 ( 2, 10) [000012] -------N--- t12 = CNS_INT long -0x43f849164b6a5490 $44
 ┌──▌ t11 long 
 ├──▌ t12 long 
N026 ( 27, 19) [000013] N---GO---U- t13 = ▌ GE long 
N027 ( 1, 1) [000015] -c--------- t15 = CNS_INT long 0 $40
 ┌──▌ t13 long 
 ├──▌ t15 long 
N028 ( 32, 21) [000016] ----GO----- t16 = ▌ EQ int <l:$34a, c:$349>
 ┌──▌ t7 int 
 ├──▌ t16 int 
N031 ( 61, 53) [000021] ---XGO-N--- ▌ TEST void 
N032 ( 63, 55) [000022] ---XGO----- JCC void cond=UEQ <l:$149, c:$148>

The EQ is removed, turning the sequence into illegal IR:

N024 ( 5, 6) [000011] ----GO---U- t11 = ▌ CAST long <- ulong <- uint <l:$248, c:$24a>
N025 ( 2, 10) [000012] -------N--- t12 = CNS_INT long -0x43f849164b6a5490 $44
 ┌──▌ t11 long 
 ├──▌ t12 long 
N026 ( 27, 19) [000013] N---GO---U- t13 = ▌ LT long 
 ┌──▌ t7 int 
 ├──▌ t13 long 
N031 ( 61, 53) [000021] ---XGO-N--- ▌ TEST void 
N032 ( 63, 55) [000022] ---XGO----- JCC void cond=UEQ