Handle more than 64 registers - Part 1 - #101950

Merged
kunalspathak merged 10 commits into
dotnet:mainfrom
kunalspathak:more-than-64-part1
May 11, 2024
Merged

Handle more than 64 registers - Part 1#101950
kunalspathak merged 10 commits into
dotnet:mainfrom
kunalspathak:more-than-64-part1

Conversation

@kunalspathak

@kunalspathakkunalspathak commented May 6, 2024

Copy link
Copy Markdown
Contributor

The general feedback for #98258 was to come up with smaller PRs concentrated around LSRA. This is part 1 of that.

For Arm64, this PR changes the typedef unsigned __int64 regMaskTP to `typedef

typedefstruct_regMaskTP
{
unsigned __int64 low;
} regMaskTP;

A version of PopCount and BitOperations has been added next to regMaskTP struct definition.

Most of the method implementation is pulled from #96196.

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label May 6, 2024
@kunalspathak

kunalspathak commented May 6, 2024

Copy link
Copy Markdown
ContributorAuthor

@dotnet/jit-contrib

@dotnet-policy-service

dotnet-policy-serviceBot commented May 6, 2024

Copy link
Copy Markdown
Contributor

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

@kunalspathak

kunalspathak commented May 7, 2024

Copy link
Copy Markdown
ContributorAuthor

This is expected to be zero TP diff, so I will investigate why it is causing 2% regression. Possibly I missed updating something:

image

@kunalspathak

kunalspathak commented May 7, 2024

Copy link
Copy Markdown
ContributorAuthor

for windows/arm64 crossgen2 collection, here is the distribution. Will take a look

??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AU_regMaskAll@@PEAVInterval@@PEAVRefPosition@@@Z : 7371109602 : NA : 24.12% : +4.3652%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@I@Z : 2298414560 : NA : 7.52% : +1.3611%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.02% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 976319605 : NA : 3.19% : +0.5782%
?mergeRegisterPreferences@Interval@@QEAAXU_regMaskAll@@@Z : 732180225 : NA : 2.40% : +0.4336%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 712437498 : NA : 2.33% : +0.4219%
?freeRegisters@LinearScan@@AEAAXU_regMaskAll@@@Z : 598599174 : NA : 1.96% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IU_regMaskAll@@@Z : 419647064 : NA : 1.37% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@@Z : 388348628 : NA : 1.27% : +0.2300%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 256572045 : +23.46% : 0.84% : +0.1519%
?gtGetRegMask@GenTree@@QEBA?AU_regMaskAll@@XZ : 247446771 : NA : 0.81% : +0.1465%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KU_regMaskAll@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.75% : +0.1357%
?addKillForRegs@LinearScan@@AEAAXU_regMaskAll@@I@Z : 103418880 : NA : 0.34% : +0.0612%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KU_regMaskAll@@@Z : 92569359 : NA : 0.30% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HU_regMaskAll@@@Z : 85318812 : NA : 0.28% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXU_regMaskAll@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.25% : +0.0446%
?emitEncodeCallGCregs@emitter@@CAXU_regMaskAll@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.24% : +0.0437%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 68804619 : NA : 0.23% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.18% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KU_regMaskAll@@1@Z : 51155804 : NA : 0.17% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.16% : +0.0298%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KU_regMaskAll@@3_N@Z : 46678609 : NA : 0.15% : +0.0276%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 46376391 : NA : 0.15% : +0.0275%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@U_regMaskAll@@PEAE@Z : 37957388 : NA : 0.12% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AU_regMaskAll@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.12% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.10% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.12% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.13% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.15% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.15% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.17% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.17% : -0.0305%
?buildUpperVectorRestoreRefPosition@LinearScan@@AEAAXPEAVInterval@@IPEAUGenTree@@_NI@Z : -62330666 : -100.00% : 0.20% : -0.0369%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.23% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.23% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.25% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.25% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.26% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.28% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.30% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.59% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.75% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.79% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.23% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.28% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 1.96% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.33% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.04% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.50% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.54% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 19.89% : -3.5995%

jakobbotsch
jakobbotsch reviewed May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h Outdated
jakobbotsch
jakobbotsch reviewed May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h Outdated
jakobbotsch
jakobbotsch reviewed May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch reviewed May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h Outdated
jakobbotsch
jakobbotsch reviewed May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h Outdated
@kunalspathak

kunalspathak commented May 9, 2024

Copy link
Copy Markdown
ContributorAuthor

The culprit was using PopCount() in genMaxOneBit() and genExactlyOneBit(). After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.

Base: 168859757414, Diff: 169865447753, +0.5956%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AUregMaskTP@@PEAVInterval@@PEAVRefPosition@@@Z : 6583187619 : NA : 22.90% : +3.8986%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@UregMaskTP@@I@Z : 1760063728 : NA : 6.12% : +1.0423%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.27% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 930438698 : NA : 3.24% : +0.5510%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 712437498 : NA : 2.48% : +0.4219%
?mergeRegisterPreferences@Interval@@QEAAXUregMaskTP@@@Z : 711153378 : NA : 2.47% : +0.4212%
?freeRegisters@LinearScan@@AEAAXUregMaskTP@@@Z : 598599174 : NA : 2.08% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IUregMaskTP@@@Z : 419548284 : NA : 1.46% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@UregMaskTP@@@Z : 388348628 : NA : 1.35% : +0.2300%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KUregMaskTP@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.80% : +0.1357%
?gtGetRegMask@GenTree@@QEBA?AUregMaskTP@@XZ : 191014321 : NA : 0.66% : +0.1131%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KUregMaskTP@@@Z : 92569359 : NA : 0.32% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HUregMaskTP@@@Z : 85318812 : NA : 0.30% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXUregMaskTP@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.26% : +0.0446%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 74404320 : +6.80% : 0.26% : +0.0441%
?emitEncodeCallGCregs@emitter@@CAXUregMaskTP@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.26% : +0.0437%
?addKillForRegs@LinearScan@@AEAAXUregMaskTP@@I@Z : 70669568 : NA : 0.25% : +0.0419%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 68804619 : NA : 0.24% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.19% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KUregMaskTP@@1@Z : 51155804 : NA : 0.18% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.18% : +0.0298%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 46376391 : NA : 0.16% : +0.0275%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KUregMaskTP@@3_N@Z : 45166929 : NA : 0.16% : +0.0267%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@UregMaskTP@@PEAE@Z : 37957388 : NA : 0.13% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AUregMaskTP@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.13% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.11% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.13% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.14% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.16% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.16% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.18% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.18% : -0.0305%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.24% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.25% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.26% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.26% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.28% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.30% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.32% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.63% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.80% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.84% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.30% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.36% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 2.08% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.48% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.23% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.79% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.89% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 21.15% : -3.5995%

@build-analysisbuild-analysisBot mentioned this pull request May 9, 2024
Closed
jakobbotsch
jakobbotsch reviewed May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp Outdated
jakobbotsch
jakobbotsch reviewed May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h Outdated
jakobbotsch
jakobbotsch reviewed May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h Outdated
jakobbotsch
jakobbotsch reviewed May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch reviewed May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h Outdated
Comment on lines +241 to +244
FORCEINLINE explicit operator unsigned int() const
{
return (unsigned int)low;
}

@jakobbotschjakobbotschMay 10, 2024

Copy link
Copy Markdown
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This one we ought to remove as well.

@kunalspathakkunalspathakMay 10, 2024

Copy link
Copy Markdown
ContributorAuthor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It is currently used only at one place. Ideally, all the *refRegs should be just gpr register set of size 4 bytes, but do not want to mix that change in this PR.

if (ig->igFlags & IGF_BYREF_REGS)
{
// Record the byref regs in front the of the instructions
*castto(id, unsigned*)++ = (unsigned)emitInitByrefRegs;
}

jakobbotsch
jakobbotsch reviewed May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h Outdated
jakobbotsch
jakobbotsch reviewed May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h Outdated
jakobbotsch
jakobbotsch reviewed May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp Outdated
Comment on lines +984 to +988
#ifdef TARGET_ARM64
regNumber regNum = (regNumber)BitScanForward(mask);
#else
regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
#endif

@jakobbotschjakobbotschMay 10, 2024

Copy link
Copy Markdown
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It would be good to avoid these ifdefs by introducing some forwarding BitScanForward in the typedef unsigned __int64 regMaskTP case.

jakobbotsch
jakobbotsch reviewed May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/lsra.h Outdated
jakobbotsch
jakobbotsch reviewed May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h Outdated
@jakobbotsch

jakobbotsch commented May 10, 2024

Copy link
Copy Markdown
Member

After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.

Yeah, seems to just be various MSVC regressions due to now having a struct instead of primitive type. Clang seems to do a little bit better. Not much we can do about that I think.

@jakobbotsch

jakobbotsch commented May 10, 2024•
edited
Loading

Copy link
Copy Markdown
Member

We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?

Alternatively we could move extra operations to live on some RegMaskOps type that operates on regMaskTP. That would probably allow all the client code to stay unified as well, even with regMaskTP typedeffed to a primitive.

@kunalspathak

kunalspathak commented May 10, 2024•
edited
Loading

Copy link
Copy Markdown
ContributorAuthor

We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?

I don't mind doing it and was advocate of similar idea back in #98258 because with that, in future, when we add APX support for Intel, enabling the "handling of 64 registers".

Edit: With that said, given that #98258 is already out for couple of months now and it is a critical work that is needed to make other progress for SVE, I would like to concentrate on enabling it with as minimal work as needed (just for arm64) and have it enable for other platforms as a follow up PRs once we complete the "predicate register" work.

jakobbotsch
jakobbotsch reviewed May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch reviewed May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h Outdated
Comment on lines +253 to +256
FORCEINLINE void setLow(uint64_t _low)
{
low = _low;
}

@jakobbotschjakobbotschMay 10, 2024

Copy link
Copy Markdown
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I don't think we should have this one (can just assign the full regMaskTP instead)

@jakobbotschjakobbotschMay 10, 2024

Copy link
Copy Markdown
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Feel free to include it in the follow up

@jakobbotschjakobbotschMay 10, 2024

Copy link
Copy Markdown
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

(FWIW, it seems like bad encapsulation to have low accessible outside this class at all)

@kunalspathakkunalspathakMay 10, 2024

Copy link
Copy Markdown
ContributorAuthor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I totally agree with you and was not a fan of having this in the last commit. May be I should just try assigning the whole regMaskTP.

@build-analysisbuild-analysisBot mentioned this pull request May 10, 2024
Closed
@kunalspathak

kunalspathak commented May 10, 2024

Copy link
Copy Markdown
ContributorAuthor

/azp run runtime-coreclr superpmi-diffs

@azure-pipelines

azure-pipelinesBot commented May 10, 2024

Copy link
Copy Markdown
Azure Pipelines successfully started running 1 pipeline(s).

@kunalspathak

kunalspathak commented May 11, 2024

Copy link
Copy Markdown
ContributorAuthor

image

@kunalspathak

kunalspathak commented May 11, 2024

Copy link
Copy Markdown
ContributorAuthor

/azp run runtime-coreclr superpmi-replay

@azure-pipelines

azure-pipelinesBot commented May 11, 2024

Copy link
Copy Markdown
Azure Pipelines successfully started running 1 pipeline(s).

@kunalspathak
kunalspathak merged commit fdc9c9d into dotnet:mainMay 11, 2024
@kunalspathak
kunalspathak deleted the more-than-64-part1 branch May 11, 2024 06:02
Ruihan-Yin pushed a commit to Ruihan-Yin/runtime that referenced this pull request May 30, 2024
@kunalspathak@Ruihan-Yin
Handle more than 64 registers - Part 1 (dotnet#101950)
20a6043
* Convert regMaskTP for ARM64 to struct with single field
* Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()
* minor fix
* review feedback
* fix the TP regression from 1.5% -> 0.5%
* Pass by value
* jit format
* review feedback
* Remove FORCEINLINE
* Remove setLow()
@github-actionsgithub-actionsBot locked and limited conversation to collaborators Jun 10, 2024
Sign up for freeto subscribe to this conversation on GitHub. Already have an account? Sign in.

Reviewers

@jakobbotschjakobbotschjakobbotsch approved these changes

Assignees

@kunalspathakkunalspathak

Labels

area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

2 participants

@kunalspathak@jakobbotsch
, 'i'); if (__m === '*' || __re.test(location.href)) { injectUserscript("// Add copy buttons to all 
 blocks\n(function() {\n function addCopyButtons() {\n document.querySelectorAll('pre code').forEach(function(codeBlock) {\n if (codeBlock.parentElement.hasAttribute('data-copy-added')) return;\n codeBlock.parentElement.setAttribute('data-copy-added', 'true');\n \n var btn = document.createElement('button');\n btn.textContent = 'Copy';\n btn.style.cssText = 'position:absolute;top:4px;right:4px;padding:2px 8px;font-size:11px;background:#4ecdc4;border:none;border-radius:4px;color:#1a1a2e;cursor:pointer;opacity:0.7;transition:opacity 0.2s;';\n btn.onmouseover = function() { this.style.opacity = '1'; };\n btn.onmouseout = function() { this.style.opacity = '0.7'; };\n btn.onclick = function() {\n navigator.clipboard.writeText(codeBlock.textContent).then(function() {\n btn.textContent = 'Copied!';\n setTimeout(function() { btn.textContent = 'Copy'; }, 1500);\n });\n };\n codeBlock.parentElement.style.position = 'relative';\n codeBlock.parentElement.appendChild(btn);\n });\n }\n \n addCopyButtons();\n \n // Re-run on dynamic content\n var observer = new MutationObserver(addCopyButtons);\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Add Copy Buttons to Code Blocks");
}
} catch(__e) { console.warn('[Userscript:Add Copy Buttons to Code Blocks]', __e); }
})();
(function(){
try {
var __m = "github.com";
var __re = new RegExp('^' + "github\\.com" + '

Skip to content
Handle more than 64 registers - Part 1 - #101950
Merged
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
May 11, 2024
Merged
Handle more than 64 registers - Part 1#101950
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
Conversation
@kunalspathak
@kunalspathakkunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
The general feedback for #98258 was to come up with smaller PRs concentrated around LSRA. This is part 1 of that.
For Arm64, this PR changes the typedef unsigned __int64 regMaskTP to `typedef
typedefstruct_regMaskTP
{
unsigned __int64 low;
} regMaskTP;
A version of PopCount and BitOperations has been added next to regMaskTP struct definition.
Most of the method implementation is pulled from #96196.
@ghostghost
added
the 
area-CodeGen-coreclr
CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
label
May 6, 2024
@kunalspathak
kunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

ContributorAuthor
@dotnet/jit-contrib
@dotnet-policy-service
dotnet-policy-serviceBot
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch

See info in area-owners.md if you want to be subscribed.
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
This is expected to be zero TP diff, so I will investigate why it is causing 2% regression. Possibly I missed updating something:
image
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
for windows/arm64 crossgen2 collection, here is the distribution. Will take a look
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AU_regMaskAll@@PEAVInterval@@PEAVRefPosition@@@Z : 7371109602 : NA : 24.12% : +4.3652%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@I@Z : 2298414560 : NA : 7.52% : +1.3611%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.02% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 976319605 : NA : 3.19% : +0.5782%
?mergeRegisterPreferences@Interval@@QEAAXU_regMaskAll@@@Z : 732180225 : NA : 2.40% : +0.4336%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 712437498 : NA : 2.33% : +0.4219%
?freeRegisters@LinearScan@@AEAAXU_regMaskAll@@@Z : 598599174 : NA : 1.96% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IU_regMaskAll@@@Z : 419647064 : NA : 1.37% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@@Z : 388348628 : NA : 1.27% : +0.2300%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 256572045 : +23.46% : 0.84% : +0.1519%
?gtGetRegMask@GenTree@@QEBA?AU_regMaskAll@@XZ : 247446771 : NA : 0.81% : +0.1465%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KU_regMaskAll@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.75% : +0.1357%
?addKillForRegs@LinearScan@@AEAAXU_regMaskAll@@I@Z : 103418880 : NA : 0.34% : +0.0612%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KU_regMaskAll@@@Z : 92569359 : NA : 0.30% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HU_regMaskAll@@@Z : 85318812 : NA : 0.28% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXU_regMaskAll@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.25% : +0.0446%
?emitEncodeCallGCregs@emitter@@CAXU_regMaskAll@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.24% : +0.0437%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 68804619 : NA : 0.23% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.18% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KU_regMaskAll@@1@Z : 51155804 : NA : 0.17% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.16% : +0.0298%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KU_regMaskAll@@3_N@Z : 46678609 : NA : 0.15% : +0.0276%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 46376391 : NA : 0.15% : +0.0275%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@U_regMaskAll@@PEAE@Z : 37957388 : NA : 0.12% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AU_regMaskAll@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.12% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.10% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.12% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.13% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.15% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.15% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.17% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.17% : -0.0305%
?buildUpperVectorRestoreRefPosition@LinearScan@@AEAAXPEAVInterval@@IPEAUGenTree@@_NI@Z : -62330666 : -100.00% : 0.20% : -0.0369%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.23% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.23% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.25% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.25% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.26% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.28% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.30% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.59% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.75% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.79% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.23% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.28% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 1.96% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.33% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.04% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.50% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.54% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 19.89% : -3.5995%

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@kunalspathak
kunalspathak
commented
May 9, 2024

Copy link


Copy Markdown

ContributorAuthor
The culprit was using PopCount() in genMaxOneBit() and genExactlyOneBit(). After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Base: 168859757414, Diff: 169865447753, +0.5956%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AUregMaskTP@@PEAVInterval@@PEAVRefPosition@@@Z : 6583187619 : NA : 22.90% : +3.8986%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@UregMaskTP@@I@Z : 1760063728 : NA : 6.12% : +1.0423%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.27% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 930438698 : NA : 3.24% : +0.5510%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 712437498 : NA : 2.48% : +0.4219%
?mergeRegisterPreferences@Interval@@QEAAXUregMaskTP@@@Z : 711153378 : NA : 2.47% : +0.4212%
?freeRegisters@LinearScan@@AEAAXUregMaskTP@@@Z : 598599174 : NA : 2.08% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IUregMaskTP@@@Z : 419548284 : NA : 1.46% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@UregMaskTP@@@Z : 388348628 : NA : 1.35% : +0.2300%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KUregMaskTP@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.80% : +0.1357%
?gtGetRegMask@GenTree@@QEBA?AUregMaskTP@@XZ : 191014321 : NA : 0.66% : +0.1131%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KUregMaskTP@@@Z : 92569359 : NA : 0.32% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HUregMaskTP@@@Z : 85318812 : NA : 0.30% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXUregMaskTP@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.26% : +0.0446%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 74404320 : +6.80% : 0.26% : +0.0441%
?emitEncodeCallGCregs@emitter@@CAXUregMaskTP@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.26% : +0.0437%
?addKillForRegs@LinearScan@@AEAAXUregMaskTP@@I@Z : 70669568 : NA : 0.25% : +0.0419%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 68804619 : NA : 0.24% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.19% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KUregMaskTP@@1@Z : 51155804 : NA : 0.18% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.18% : +0.0298%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 46376391 : NA : 0.16% : +0.0275%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KUregMaskTP@@3_N@Z : 45166929 : NA : 0.16% : +0.0267%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@UregMaskTP@@PEAE@Z : 37957388 : NA : 0.13% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AUregMaskTP@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.13% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.11% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.13% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.14% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.16% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.16% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.18% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.18% : -0.0305%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.24% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.25% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.26% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.26% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.28% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.30% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.32% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.63% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.80% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.84% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.30% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.36% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 2.08% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.48% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.23% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.79% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.89% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 21.15% : -3.5995%

@build-analysisbuild-analysisBot
mentioned this pull request
May 9, 2024

Closed

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+241
 to 
+244

 FORCEINLINE explicit operator unsigned int() const
 {
 return (unsigned int)low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This one we ought to remove as well.
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It is currently used only at one place. Ideally, all the *refRegs should be just gpr register set of size 4 bytes, but do not want to mix that change in this PR.
if (ig->igFlags & IGF_BYREF_REGS)
{
// Record the byref regs in front the of the instructions
*castto(id, unsigned*)++ = (unsigned)emitInitByrefRegs;
}
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated


Comment on lines

+984
 to 
+988

#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)BitScanForward(mask);
#else
 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
#endif
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It would be good to avoid these ifdefs by introducing some forwarding BitScanForward in the typedef unsigned __int64 regMaskTP case.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/lsra.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@jakobbotsch
jakobbotsch
commented
May 10, 2024

Copy link


Copy Markdown

Member
After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Yeah, seems to just be various MSVC regressions due to now having a struct instead of primitive type. Clang seems to do a little bit better. Not much we can do about that I think.
@jakobbotsch
jakobbotsch
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

Member
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
Alternatively we could move extra operations to live on some RegMaskOps type that operates on regMaskTP. That would probably allow all the client code to stay unified as well, even with regMaskTP typedeffed to a primitive.
@kunalspathak
kunalspathak
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

ContributorAuthor
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
I don't mind doing it and was advocate of similar idea back in #98258 because with that, in future, when we add APX support for Intel, enabling the "handling of 64 registers".
Edit: With that said, given that #98258 is already out for couple of months now and it is a critical work that is needed to make other progress for SVE, I would like to concentrate on enabling it with as minimal work as needed (just for arm64) and have it enable for other platforms as a follow up PRs once we complete the "predicate register" work.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+253
 to 
+256

 FORCEINLINE void setLow(uint64_t _low)
 {
 low = _low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I don't think we should have this one (can just assign the full regMaskTP instead)
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Feel free to include it in the follow up
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

(FWIW, it seems like bad encapsulation to have low accessible outside this class at all)
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I totally agree with you and was not a fan of having this in the last commit. May be I should just try assigning the whole regMaskTP.
@build-analysisbuild-analysisBot
mentioned this pull request
May 10, 2024

Closed

@kunalspathak
kunalspathak
commented
May 10, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-diffs
@azure-pipelines
azure-pipelinesBot
commented
May 10, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
image
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-replay
@azure-pipelines
azure-pipelinesBot
commented
May 11, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
merged commit fdc9c9d
into
dotnet:mainMay 11, 2024
@kunalspathak
kunalspathak
deleted the

more-than-64-part1

branch
May 11, 2024 06:02
Ruihan-Yin pushed a commit
to Ruihan-Yin/runtime
that referenced
this pull request
May 30, 2024
@kunalspathak@Ruihan-Yin
Handle more than 64 registers - Part 1 (dotnet#101950)
20a6043
* Convert regMaskTP for ARM64 to struct with single field
* Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()
* minor fix
* review feedback
* fix the TP regression from 1.5% -> 0.5%
* Pass by value
* jit format
* review feedback
* Remove FORCEINLINE
* Remove setLow()
@github-actionsgithub-actionsBot
locked and limited conversation to collaborators
Jun 10, 2024
Sign up for freeto subscribe to this conversation on GitHub.
Already have an account?
Sign in.


Reviewers

@jakobbotschjakobbotschjakobbotsch approved these changes

Assignees

@kunalspathakkunalspathak

Labels

area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

Projects


None yet


Milestone


No milestone


Development

Successfully merging this pull request may close these issues.

2 participants

@kunalspathak@jakobbotsch

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Force GitHub README to respect dark mode\n(function() {\n var style = document.createElement('style');\n style.textContent = '\n .markdown-body {\n color-scheme: dark light;\n }\n .markdown-body pre { background: #161b22 !important; }\n .markdown-body code { background: rgba(110, 118, 129, 0.4) !important; }\n .markdown-body table th, .markdown-body table td { border-color: #30363d !important; }\n .markdown-body img { background: #0d1117; }\n .markdown-body blockquote { border-left-color: #8b949e; }\n .markdown-body hr { border-color: #30363d; }\n ';\n document.head.appendChild(style);\n})();", "GitHub Dark Mode README Fix");
}
} catch(__e) { console.warn('[Userscript:GitHub Dark Mode README Fix]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
Handle more than 64 registers - Part 1 - #101950
Merged
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
May 11, 2024
Merged
Handle more than 64 registers - Part 1#101950
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
Conversation
@kunalspathak
@kunalspathakkunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
The general feedback for #98258 was to come up with smaller PRs concentrated around LSRA. This is part 1 of that.
For Arm64, this PR changes the typedef unsigned __int64 regMaskTP to `typedef
typedefstruct_regMaskTP
{
unsigned __int64 low;
} regMaskTP;
A version of PopCount and BitOperations has been added next to regMaskTP struct definition.
Most of the method implementation is pulled from #96196.
@ghostghost
added
the 
area-CodeGen-coreclr
CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
label
May 6, 2024
@kunalspathak
kunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

ContributorAuthor
@dotnet/jit-contrib
@dotnet-policy-service
dotnet-policy-serviceBot
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch

See info in area-owners.md if you want to be subscribed.
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
This is expected to be zero TP diff, so I will investigate why it is causing 2% regression. Possibly I missed updating something:
image
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
for windows/arm64 crossgen2 collection, here is the distribution. Will take a look
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AU_regMaskAll@@PEAVInterval@@PEAVRefPosition@@@Z : 7371109602 : NA : 24.12% : +4.3652%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@I@Z : 2298414560 : NA : 7.52% : +1.3611%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.02% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 976319605 : NA : 3.19% : +0.5782%
?mergeRegisterPreferences@Interval@@QEAAXU_regMaskAll@@@Z : 732180225 : NA : 2.40% : +0.4336%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 712437498 : NA : 2.33% : +0.4219%
?freeRegisters@LinearScan@@AEAAXU_regMaskAll@@@Z : 598599174 : NA : 1.96% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IU_regMaskAll@@@Z : 419647064 : NA : 1.37% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@@Z : 388348628 : NA : 1.27% : +0.2300%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 256572045 : +23.46% : 0.84% : +0.1519%
?gtGetRegMask@GenTree@@QEBA?AU_regMaskAll@@XZ : 247446771 : NA : 0.81% : +0.1465%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KU_regMaskAll@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.75% : +0.1357%
?addKillForRegs@LinearScan@@AEAAXU_regMaskAll@@I@Z : 103418880 : NA : 0.34% : +0.0612%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KU_regMaskAll@@@Z : 92569359 : NA : 0.30% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HU_regMaskAll@@@Z : 85318812 : NA : 0.28% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXU_regMaskAll@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.25% : +0.0446%
?emitEncodeCallGCregs@emitter@@CAXU_regMaskAll@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.24% : +0.0437%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 68804619 : NA : 0.23% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.18% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KU_regMaskAll@@1@Z : 51155804 : NA : 0.17% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.16% : +0.0298%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KU_regMaskAll@@3_N@Z : 46678609 : NA : 0.15% : +0.0276%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 46376391 : NA : 0.15% : +0.0275%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@U_regMaskAll@@PEAE@Z : 37957388 : NA : 0.12% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AU_regMaskAll@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.12% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.10% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.12% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.13% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.15% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.15% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.17% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.17% : -0.0305%
?buildUpperVectorRestoreRefPosition@LinearScan@@AEAAXPEAVInterval@@IPEAUGenTree@@_NI@Z : -62330666 : -100.00% : 0.20% : -0.0369%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.23% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.23% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.25% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.25% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.26% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.28% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.30% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.59% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.75% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.79% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.23% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.28% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 1.96% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.33% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.04% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.50% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.54% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 19.89% : -3.5995%

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@kunalspathak
kunalspathak
commented
May 9, 2024

Copy link


Copy Markdown

ContributorAuthor
The culprit was using PopCount() in genMaxOneBit() and genExactlyOneBit(). After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Base: 168859757414, Diff: 169865447753, +0.5956%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AUregMaskTP@@PEAVInterval@@PEAVRefPosition@@@Z : 6583187619 : NA : 22.90% : +3.8986%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@UregMaskTP@@I@Z : 1760063728 : NA : 6.12% : +1.0423%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.27% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 930438698 : NA : 3.24% : +0.5510%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 712437498 : NA : 2.48% : +0.4219%
?mergeRegisterPreferences@Interval@@QEAAXUregMaskTP@@@Z : 711153378 : NA : 2.47% : +0.4212%
?freeRegisters@LinearScan@@AEAAXUregMaskTP@@@Z : 598599174 : NA : 2.08% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IUregMaskTP@@@Z : 419548284 : NA : 1.46% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@UregMaskTP@@@Z : 388348628 : NA : 1.35% : +0.2300%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KUregMaskTP@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.80% : +0.1357%
?gtGetRegMask@GenTree@@QEBA?AUregMaskTP@@XZ : 191014321 : NA : 0.66% : +0.1131%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KUregMaskTP@@@Z : 92569359 : NA : 0.32% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HUregMaskTP@@@Z : 85318812 : NA : 0.30% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXUregMaskTP@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.26% : +0.0446%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 74404320 : +6.80% : 0.26% : +0.0441%
?emitEncodeCallGCregs@emitter@@CAXUregMaskTP@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.26% : +0.0437%
?addKillForRegs@LinearScan@@AEAAXUregMaskTP@@I@Z : 70669568 : NA : 0.25% : +0.0419%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 68804619 : NA : 0.24% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.19% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KUregMaskTP@@1@Z : 51155804 : NA : 0.18% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.18% : +0.0298%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 46376391 : NA : 0.16% : +0.0275%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KUregMaskTP@@3_N@Z : 45166929 : NA : 0.16% : +0.0267%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@UregMaskTP@@PEAE@Z : 37957388 : NA : 0.13% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AUregMaskTP@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.13% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.11% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.13% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.14% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.16% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.16% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.18% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.18% : -0.0305%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.24% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.25% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.26% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.26% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.28% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.30% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.32% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.63% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.80% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.84% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.30% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.36% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 2.08% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.48% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.23% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.79% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.89% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 21.15% : -3.5995%

@build-analysisbuild-analysisBot
mentioned this pull request
May 9, 2024

Closed

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+241
 to 
+244

 FORCEINLINE explicit operator unsigned int() const
 {
 return (unsigned int)low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This one we ought to remove as well.
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It is currently used only at one place. Ideally, all the *refRegs should be just gpr register set of size 4 bytes, but do not want to mix that change in this PR.
if (ig->igFlags & IGF_BYREF_REGS)
{
// Record the byref regs in front the of the instructions
*castto(id, unsigned*)++ = (unsigned)emitInitByrefRegs;
}
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated


Comment on lines

+984
 to 
+988

#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)BitScanForward(mask);
#else
 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
#endif
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It would be good to avoid these ifdefs by introducing some forwarding BitScanForward in the typedef unsigned __int64 regMaskTP case.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/lsra.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@jakobbotsch
jakobbotsch
commented
May 10, 2024

Copy link


Copy Markdown

Member
After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Yeah, seems to just be various MSVC regressions due to now having a struct instead of primitive type. Clang seems to do a little bit better. Not much we can do about that I think.
@jakobbotsch
jakobbotsch
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

Member
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
Alternatively we could move extra operations to live on some RegMaskOps type that operates on regMaskTP. That would probably allow all the client code to stay unified as well, even with regMaskTP typedeffed to a primitive.
@kunalspathak
kunalspathak
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

ContributorAuthor
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
I don't mind doing it and was advocate of similar idea back in #98258 because with that, in future, when we add APX support for Intel, enabling the "handling of 64 registers".
Edit: With that said, given that #98258 is already out for couple of months now and it is a critical work that is needed to make other progress for SVE, I would like to concentrate on enabling it with as minimal work as needed (just for arm64) and have it enable for other platforms as a follow up PRs once we complete the "predicate register" work.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+253
 to 
+256

 FORCEINLINE void setLow(uint64_t _low)
 {
 low = _low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I don't think we should have this one (can just assign the full regMaskTP instead)
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Feel free to include it in the follow up
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

(FWIW, it seems like bad encapsulation to have low accessible outside this class at all)
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I totally agree with you and was not a fan of having this in the last commit. May be I should just try assigning the whole regMaskTP.
@build-analysisbuild-analysisBot
mentioned this pull request
May 10, 2024

Closed

@kunalspathak
kunalspathak
commented
May 10, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-diffs
@azure-pipelines
azure-pipelinesBot
commented
May 10, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
image
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-replay
@azure-pipelines
azure-pipelinesBot
commented
May 11, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
merged commit fdc9c9d
into
dotnet:mainMay 11, 2024
@kunalspathak
kunalspathak
deleted the

more-than-64-part1

branch
May 11, 2024 06:02
Ruihan-Yin pushed a commit
to Ruihan-Yin/runtime
that referenced
this pull request
May 30, 2024
@kunalspathak@Ruihan-Yin
Handle more than 64 registers - Part 1 (dotnet#101950)
20a6043
* Convert regMaskTP for ARM64 to struct with single field
* Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()
* minor fix
* review feedback
* fix the TP regression from 1.5% -> 0.5%
* Pass by value
* jit format
* review feedback
* Remove FORCEINLINE
* Remove setLow()
@github-actionsgithub-actionsBot
locked and limited conversation to collaborators
Jun 10, 2024
Sign up for freeto subscribe to this conversation on GitHub.
Already have an account?
Sign in.


Reviewers

@jakobbotschjakobbotschjakobbotsch approved these changes

Assignees

@kunalspathakkunalspathak

Labels

area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

Projects


None yet


Milestone


No milestone


Development

Successfully merging this pull request may close these issues.

2 participants

@kunalspathak@jakobbotsch

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Highlight search terms from Google/DuckDuckGo/Bing referrer\n(function() {\n var ref = document.referrer;\n var terms = [];\n \n if (ref.includes('google.com') || ref.includes('duckduckgo.com') || ref.includes('bing.com')) {\n var url = new URL(ref);\n var q = url.searchParams.get('q') || url.searchParams.get('p');\n if (q) {\n terms = q.split(/\\s+/).filter(function(t) { return t.length > 2; });\n }\n }\n \n if (terms.length === 0) return;\n \n var style = document.createElement('style');\n style.textContent = '.userscript-highlight { background: #fbbf24; color: #1a1a2e; padding: 1px 3px; border-radius: 2px; }';\n document.head.appendChild(style);\n \n function highlight(node) {\n if (node.nodeType === 3) { // text node\n var text = node.textContent;\n var found = false;\n terms.forEach(function(term) {\n var regex = new RegExp('(' + term.replace(/[.*+?^${}()|[\\]\\\\]/g, '\\\\') + ')', 'gi');\n if (regex.test(text)) {\n found = true;\n var frag = document.createDocumentFragment();\n var parts = text.split(regex);\n parts.forEach(function(part, i) {\n if (i % 2 === 0) {\n frag.appendChild(document.createTextNode(part));\n } else {\n var span = document.createElement('span');\n span.className = 'userscript-highlight';\n span.textContent = part;\n frag.appendChild(span);\n }\n });\n node.parentNode.replaceChild(frag, node);\n }\n });\n } else if (node.nodeType === 1 && node.childNodes) { // element\n var skipTags = ['SCRIPT', 'STYLE', 'NOSCRIPT', 'TEXTAREA', 'INPUT', 'SELECT'];\n if (!skipTags.includes(node.tagName)) {\n Array.from(node.childNodes).forEach(highlight);\n }\n }\n }\n \n highlight(document.body);\n \n // Re-highlight on dynamic content\n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1 || node.nodeType === 3) highlight(node);\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Highlight Search Terms");
}
} catch(__e) { console.warn('[Userscript:Highlight Search Terms]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
Handle more than 64 registers - Part 1 - #101950
Merged
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
May 11, 2024
Merged
Handle more than 64 registers - Part 1#101950
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
Conversation
@kunalspathak
@kunalspathakkunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
The general feedback for #98258 was to come up with smaller PRs concentrated around LSRA. This is part 1 of that.
For Arm64, this PR changes the typedef unsigned __int64 regMaskTP to `typedef
typedefstruct_regMaskTP
{
unsigned __int64 low;
} regMaskTP;
A version of PopCount and BitOperations has been added next to regMaskTP struct definition.
Most of the method implementation is pulled from #96196.
@ghostghost
added
the 
area-CodeGen-coreclr
CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
label
May 6, 2024
@kunalspathak
kunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

ContributorAuthor
@dotnet/jit-contrib
@dotnet-policy-service
dotnet-policy-serviceBot
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch

See info in area-owners.md if you want to be subscribed.
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
This is expected to be zero TP diff, so I will investigate why it is causing 2% regression. Possibly I missed updating something:
image
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
for windows/arm64 crossgen2 collection, here is the distribution. Will take a look
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AU_regMaskAll@@PEAVInterval@@PEAVRefPosition@@@Z : 7371109602 : NA : 24.12% : +4.3652%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@I@Z : 2298414560 : NA : 7.52% : +1.3611%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.02% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 976319605 : NA : 3.19% : +0.5782%
?mergeRegisterPreferences@Interval@@QEAAXU_regMaskAll@@@Z : 732180225 : NA : 2.40% : +0.4336%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 712437498 : NA : 2.33% : +0.4219%
?freeRegisters@LinearScan@@AEAAXU_regMaskAll@@@Z : 598599174 : NA : 1.96% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IU_regMaskAll@@@Z : 419647064 : NA : 1.37% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@@Z : 388348628 : NA : 1.27% : +0.2300%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 256572045 : +23.46% : 0.84% : +0.1519%
?gtGetRegMask@GenTree@@QEBA?AU_regMaskAll@@XZ : 247446771 : NA : 0.81% : +0.1465%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KU_regMaskAll@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.75% : +0.1357%
?addKillForRegs@LinearScan@@AEAAXU_regMaskAll@@I@Z : 103418880 : NA : 0.34% : +0.0612%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KU_regMaskAll@@@Z : 92569359 : NA : 0.30% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HU_regMaskAll@@@Z : 85318812 : NA : 0.28% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXU_regMaskAll@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.25% : +0.0446%
?emitEncodeCallGCregs@emitter@@CAXU_regMaskAll@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.24% : +0.0437%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 68804619 : NA : 0.23% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.18% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KU_regMaskAll@@1@Z : 51155804 : NA : 0.17% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.16% : +0.0298%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KU_regMaskAll@@3_N@Z : 46678609 : NA : 0.15% : +0.0276%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 46376391 : NA : 0.15% : +0.0275%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@U_regMaskAll@@PEAE@Z : 37957388 : NA : 0.12% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AU_regMaskAll@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.12% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.10% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.12% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.13% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.15% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.15% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.17% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.17% : -0.0305%
?buildUpperVectorRestoreRefPosition@LinearScan@@AEAAXPEAVInterval@@IPEAUGenTree@@_NI@Z : -62330666 : -100.00% : 0.20% : -0.0369%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.23% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.23% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.25% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.25% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.26% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.28% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.30% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.59% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.75% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.79% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.23% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.28% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 1.96% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.33% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.04% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.50% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.54% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 19.89% : -3.5995%

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@kunalspathak
kunalspathak
commented
May 9, 2024

Copy link


Copy Markdown

ContributorAuthor
The culprit was using PopCount() in genMaxOneBit() and genExactlyOneBit(). After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Base: 168859757414, Diff: 169865447753, +0.5956%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AUregMaskTP@@PEAVInterval@@PEAVRefPosition@@@Z : 6583187619 : NA : 22.90% : +3.8986%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@UregMaskTP@@I@Z : 1760063728 : NA : 6.12% : +1.0423%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.27% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 930438698 : NA : 3.24% : +0.5510%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 712437498 : NA : 2.48% : +0.4219%
?mergeRegisterPreferences@Interval@@QEAAXUregMaskTP@@@Z : 711153378 : NA : 2.47% : +0.4212%
?freeRegisters@LinearScan@@AEAAXUregMaskTP@@@Z : 598599174 : NA : 2.08% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IUregMaskTP@@@Z : 419548284 : NA : 1.46% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@UregMaskTP@@@Z : 388348628 : NA : 1.35% : +0.2300%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KUregMaskTP@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.80% : +0.1357%
?gtGetRegMask@GenTree@@QEBA?AUregMaskTP@@XZ : 191014321 : NA : 0.66% : +0.1131%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KUregMaskTP@@@Z : 92569359 : NA : 0.32% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HUregMaskTP@@@Z : 85318812 : NA : 0.30% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXUregMaskTP@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.26% : +0.0446%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 74404320 : +6.80% : 0.26% : +0.0441%
?emitEncodeCallGCregs@emitter@@CAXUregMaskTP@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.26% : +0.0437%
?addKillForRegs@LinearScan@@AEAAXUregMaskTP@@I@Z : 70669568 : NA : 0.25% : +0.0419%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 68804619 : NA : 0.24% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.19% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KUregMaskTP@@1@Z : 51155804 : NA : 0.18% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.18% : +0.0298%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 46376391 : NA : 0.16% : +0.0275%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KUregMaskTP@@3_N@Z : 45166929 : NA : 0.16% : +0.0267%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@UregMaskTP@@PEAE@Z : 37957388 : NA : 0.13% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AUregMaskTP@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.13% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.11% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.13% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.14% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.16% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.16% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.18% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.18% : -0.0305%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.24% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.25% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.26% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.26% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.28% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.30% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.32% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.63% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.80% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.84% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.30% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.36% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 2.08% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.48% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.23% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.79% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.89% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 21.15% : -3.5995%

@build-analysisbuild-analysisBot
mentioned this pull request
May 9, 2024

Closed

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+241
 to 
+244

 FORCEINLINE explicit operator unsigned int() const
 {
 return (unsigned int)low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This one we ought to remove as well.
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It is currently used only at one place. Ideally, all the *refRegs should be just gpr register set of size 4 bytes, but do not want to mix that change in this PR.
if (ig->igFlags & IGF_BYREF_REGS)
{
// Record the byref regs in front the of the instructions
*castto(id, unsigned*)++ = (unsigned)emitInitByrefRegs;
}
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated


Comment on lines

+984
 to 
+988

#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)BitScanForward(mask);
#else
 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
#endif
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It would be good to avoid these ifdefs by introducing some forwarding BitScanForward in the typedef unsigned __int64 regMaskTP case.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/lsra.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@jakobbotsch
jakobbotsch
commented
May 10, 2024

Copy link


Copy Markdown

Member
After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Yeah, seems to just be various MSVC regressions due to now having a struct instead of primitive type. Clang seems to do a little bit better. Not much we can do about that I think.
@jakobbotsch
jakobbotsch
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

Member
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
Alternatively we could move extra operations to live on some RegMaskOps type that operates on regMaskTP. That would probably allow all the client code to stay unified as well, even with regMaskTP typedeffed to a primitive.
@kunalspathak
kunalspathak
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

ContributorAuthor
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
I don't mind doing it and was advocate of similar idea back in #98258 because with that, in future, when we add APX support for Intel, enabling the "handling of 64 registers".
Edit: With that said, given that #98258 is already out for couple of months now and it is a critical work that is needed to make other progress for SVE, I would like to concentrate on enabling it with as minimal work as needed (just for arm64) and have it enable for other platforms as a follow up PRs once we complete the "predicate register" work.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+253
 to 
+256

 FORCEINLINE void setLow(uint64_t _low)
 {
 low = _low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I don't think we should have this one (can just assign the full regMaskTP instead)
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Feel free to include it in the follow up
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

(FWIW, it seems like bad encapsulation to have low accessible outside this class at all)
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I totally agree with you and was not a fan of having this in the last commit. May be I should just try assigning the whole regMaskTP.
@build-analysisbuild-analysisBot
mentioned this pull request
May 10, 2024

Closed

@kunalspathak
kunalspathak
commented
May 10, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-diffs
@azure-pipelines
azure-pipelinesBot
commented
May 10, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
image
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-replay
@azure-pipelines
azure-pipelinesBot
commented
May 11, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
merged commit fdc9c9d
into
dotnet:mainMay 11, 2024
@kunalspathak
kunalspathak
deleted the

more-than-64-part1

branch
May 11, 2024 06:02
Ruihan-Yin pushed a commit
to Ruihan-Yin/runtime
that referenced
this pull request
May 30, 2024
@kunalspathak@Ruihan-Yin
Handle more than 64 registers - Part 1 (dotnet#101950)
20a6043
* Convert regMaskTP for ARM64 to struct with single field
* Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()
* minor fix
* review feedback
* fix the TP regression from 1.5% -> 0.5%
* Pass by value
* jit format
* review feedback
* Remove FORCEINLINE
* Remove setLow()
@github-actionsgithub-actionsBot
locked and limited conversation to collaborators
Jun 10, 2024
Sign up for freeto subscribe to this conversation on GitHub.
Already have an account?
Sign in.


Reviewers

@jakobbotschjakobbotschjakobbotsch approved these changes

Assignees

@kunalspathakkunalspathak

Labels

area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

Projects


None yet


Milestone


No milestone


Development

Successfully merging this pull request may close these issues.

2 participants

@kunalspathak@jakobbotsch

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Strip utm_, fbclid, gclid, etc. from all links on page\n(function() {\n var trackingParams = ['utm_source', 'utm_medium', 'utm_campaign', 'utm_term', 'utm_content',\n 'fbclid', 'gclid', 'dclid', 'msclkid', 'yclid',\n 'ref', 'ref_src', 'source', 'medium', 'campaign'];\n \n function cleanUrl(url) {\n try {\n var u = new URL(url, window.location.origin);\n var changed = false;\n trackingParams.forEach(function(p) {\n if (u.searchParams.has(p)) {\n u.searchParams.delete(p);\n changed = true;\n }\n });\n return changed ? u.toString() : url;\n } catch (e) {\n return url;\n }\n }\n \n function cleanLinks() {\n document.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n \n cleanLinks();\n \n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1) {\n if (node.tagName === 'A') cleanLinks();\n node.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Remove Tracking Parameters from Links");
}
} catch(__e) { console.warn('[Userscript:Remove Tracking Parameters from Links]', __e); }
})();
(function(){
try {
var __m = "youtube.com";
var __re = new RegExp('^' + "youtube\\.com" + '

Skip to content
Handle more than 64 registers - Part 1 - #101950
Merged
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
May 11, 2024
Merged
Handle more than 64 registers - Part 1#101950
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
Conversation
@kunalspathak
@kunalspathakkunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
The general feedback for #98258 was to come up with smaller PRs concentrated around LSRA. This is part 1 of that.
For Arm64, this PR changes the typedef unsigned __int64 regMaskTP to `typedef
typedefstruct_regMaskTP
{
unsigned __int64 low;
} regMaskTP;
A version of PopCount and BitOperations has been added next to regMaskTP struct definition.
Most of the method implementation is pulled from #96196.
@ghostghost
added
the 
area-CodeGen-coreclr
CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
label
May 6, 2024
@kunalspathak
kunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

ContributorAuthor
@dotnet/jit-contrib
@dotnet-policy-service
dotnet-policy-serviceBot
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch

See info in area-owners.md if you want to be subscribed.
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
This is expected to be zero TP diff, so I will investigate why it is causing 2% regression. Possibly I missed updating something:
image
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
for windows/arm64 crossgen2 collection, here is the distribution. Will take a look
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AU_regMaskAll@@PEAVInterval@@PEAVRefPosition@@@Z : 7371109602 : NA : 24.12% : +4.3652%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@I@Z : 2298414560 : NA : 7.52% : +1.3611%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.02% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 976319605 : NA : 3.19% : +0.5782%
?mergeRegisterPreferences@Interval@@QEAAXU_regMaskAll@@@Z : 732180225 : NA : 2.40% : +0.4336%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 712437498 : NA : 2.33% : +0.4219%
?freeRegisters@LinearScan@@AEAAXU_regMaskAll@@@Z : 598599174 : NA : 1.96% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IU_regMaskAll@@@Z : 419647064 : NA : 1.37% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@@Z : 388348628 : NA : 1.27% : +0.2300%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 256572045 : +23.46% : 0.84% : +0.1519%
?gtGetRegMask@GenTree@@QEBA?AU_regMaskAll@@XZ : 247446771 : NA : 0.81% : +0.1465%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KU_regMaskAll@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.75% : +0.1357%
?addKillForRegs@LinearScan@@AEAAXU_regMaskAll@@I@Z : 103418880 : NA : 0.34% : +0.0612%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KU_regMaskAll@@@Z : 92569359 : NA : 0.30% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HU_regMaskAll@@@Z : 85318812 : NA : 0.28% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXU_regMaskAll@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.25% : +0.0446%
?emitEncodeCallGCregs@emitter@@CAXU_regMaskAll@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.24% : +0.0437%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 68804619 : NA : 0.23% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.18% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KU_regMaskAll@@1@Z : 51155804 : NA : 0.17% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.16% : +0.0298%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KU_regMaskAll@@3_N@Z : 46678609 : NA : 0.15% : +0.0276%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 46376391 : NA : 0.15% : +0.0275%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@U_regMaskAll@@PEAE@Z : 37957388 : NA : 0.12% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AU_regMaskAll@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.12% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.10% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.12% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.13% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.15% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.15% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.17% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.17% : -0.0305%
?buildUpperVectorRestoreRefPosition@LinearScan@@AEAAXPEAVInterval@@IPEAUGenTree@@_NI@Z : -62330666 : -100.00% : 0.20% : -0.0369%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.23% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.23% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.25% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.25% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.26% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.28% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.30% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.59% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.75% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.79% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.23% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.28% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 1.96% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.33% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.04% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.50% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.54% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 19.89% : -3.5995%

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@kunalspathak
kunalspathak
commented
May 9, 2024

Copy link


Copy Markdown

ContributorAuthor
The culprit was using PopCount() in genMaxOneBit() and genExactlyOneBit(). After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Base: 168859757414, Diff: 169865447753, +0.5956%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AUregMaskTP@@PEAVInterval@@PEAVRefPosition@@@Z : 6583187619 : NA : 22.90% : +3.8986%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@UregMaskTP@@I@Z : 1760063728 : NA : 6.12% : +1.0423%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.27% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 930438698 : NA : 3.24% : +0.5510%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 712437498 : NA : 2.48% : +0.4219%
?mergeRegisterPreferences@Interval@@QEAAXUregMaskTP@@@Z : 711153378 : NA : 2.47% : +0.4212%
?freeRegisters@LinearScan@@AEAAXUregMaskTP@@@Z : 598599174 : NA : 2.08% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IUregMaskTP@@@Z : 419548284 : NA : 1.46% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@UregMaskTP@@@Z : 388348628 : NA : 1.35% : +0.2300%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KUregMaskTP@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.80% : +0.1357%
?gtGetRegMask@GenTree@@QEBA?AUregMaskTP@@XZ : 191014321 : NA : 0.66% : +0.1131%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KUregMaskTP@@@Z : 92569359 : NA : 0.32% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HUregMaskTP@@@Z : 85318812 : NA : 0.30% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXUregMaskTP@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.26% : +0.0446%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 74404320 : +6.80% : 0.26% : +0.0441%
?emitEncodeCallGCregs@emitter@@CAXUregMaskTP@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.26% : +0.0437%
?addKillForRegs@LinearScan@@AEAAXUregMaskTP@@I@Z : 70669568 : NA : 0.25% : +0.0419%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 68804619 : NA : 0.24% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.19% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KUregMaskTP@@1@Z : 51155804 : NA : 0.18% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.18% : +0.0298%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 46376391 : NA : 0.16% : +0.0275%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KUregMaskTP@@3_N@Z : 45166929 : NA : 0.16% : +0.0267%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@UregMaskTP@@PEAE@Z : 37957388 : NA : 0.13% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AUregMaskTP@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.13% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.11% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.13% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.14% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.16% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.16% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.18% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.18% : -0.0305%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.24% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.25% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.26% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.26% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.28% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.30% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.32% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.63% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.80% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.84% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.30% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.36% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 2.08% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.48% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.23% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.79% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.89% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 21.15% : -3.5995%

@build-analysisbuild-analysisBot
mentioned this pull request
May 9, 2024

Closed

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+241
 to 
+244

 FORCEINLINE explicit operator unsigned int() const
 {
 return (unsigned int)low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This one we ought to remove as well.
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It is currently used only at one place. Ideally, all the *refRegs should be just gpr register set of size 4 bytes, but do not want to mix that change in this PR.
if (ig->igFlags & IGF_BYREF_REGS)
{
// Record the byref regs in front the of the instructions
*castto(id, unsigned*)++ = (unsigned)emitInitByrefRegs;
}
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated


Comment on lines

+984
 to 
+988

#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)BitScanForward(mask);
#else
 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
#endif
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It would be good to avoid these ifdefs by introducing some forwarding BitScanForward in the typedef unsigned __int64 regMaskTP case.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/lsra.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@jakobbotsch
jakobbotsch
commented
May 10, 2024

Copy link


Copy Markdown

Member
After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Yeah, seems to just be various MSVC regressions due to now having a struct instead of primitive type. Clang seems to do a little bit better. Not much we can do about that I think.
@jakobbotsch
jakobbotsch
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

Member
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
Alternatively we could move extra operations to live on some RegMaskOps type that operates on regMaskTP. That would probably allow all the client code to stay unified as well, even with regMaskTP typedeffed to a primitive.
@kunalspathak
kunalspathak
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

ContributorAuthor
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
I don't mind doing it and was advocate of similar idea back in #98258 because with that, in future, when we add APX support for Intel, enabling the "handling of 64 registers".
Edit: With that said, given that #98258 is already out for couple of months now and it is a critical work that is needed to make other progress for SVE, I would like to concentrate on enabling it with as minimal work as needed (just for arm64) and have it enable for other platforms as a follow up PRs once we complete the "predicate register" work.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+253
 to 
+256

 FORCEINLINE void setLow(uint64_t _low)
 {
 low = _low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I don't think we should have this one (can just assign the full regMaskTP instead)
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Feel free to include it in the follow up
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

(FWIW, it seems like bad encapsulation to have low accessible outside this class at all)
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I totally agree with you and was not a fan of having this in the last commit. May be I should just try assigning the whole regMaskTP.
@build-analysisbuild-analysisBot
mentioned this pull request
May 10, 2024

Closed

@kunalspathak
kunalspathak
commented
May 10, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-diffs
@azure-pipelines
azure-pipelinesBot
commented
May 10, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
image
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-replay
@azure-pipelines
azure-pipelinesBot
commented
May 11, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
merged commit fdc9c9d
into
dotnet:mainMay 11, 2024
@kunalspathak
kunalspathak
deleted the

more-than-64-part1

branch
May 11, 2024 06:02
Ruihan-Yin pushed a commit
to Ruihan-Yin/runtime
that referenced
this pull request
May 30, 2024
@kunalspathak@Ruihan-Yin
Handle more than 64 registers - Part 1 (dotnet#101950)
20a6043
* Convert regMaskTP for ARM64 to struct with single field
* Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()
* minor fix
* review feedback
* fix the TP regression from 1.5% -> 0.5%
* Pass by value
* jit format
* review feedback
* Remove FORCEINLINE
* Remove setLow()
@github-actionsgithub-actionsBot
locked and limited conversation to collaborators
Jun 10, 2024
Sign up for freeto subscribe to this conversation on GitHub.
Already have an account?
Sign in.


Reviewers

@jakobbotschjakobbotschjakobbotsch approved these changes

Assignees

@kunalspathakkunalspathak

Labels

area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

Projects


None yet


Milestone


No milestone


Development

Successfully merging this pull request may close these issues.

2 participants

@kunalspathak@jakobbotsch

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Auto-enable theater mode on YouTube\n(function() {\n function tryTheater() {\n var btn = document.querySelector('button[aria-label=\"Theater mode\"], ytd-player #player button[title=\"Theater mode\"]');\n if (btn && !btn.classList.contains('activated')) {\n btn.click();\n }\n }\n \n // Try immediately\n tryTheater();\n \n // Try after navigation (SPA)\n var lastUrl = location.href;\n setInterval(function() {\n if (location.href !== lastUrl) {\n lastUrl = location.href;\n setTimeout(tryTheater, 500);\n }\n }, 1000);\n \n // Also try on player load\n var observer = new MutationObserver(tryTheater);\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "YouTube Theater Mode Default");
}
} catch(__e) { console.warn('[Userscript:YouTube Theater Mode Default]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
Handle more than 64 registers - Part 1 - #101950
Merged
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
May 11, 2024
Merged
Handle more than 64 registers - Part 1#101950
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
Conversation
@kunalspathak
@kunalspathakkunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
The general feedback for #98258 was to come up with smaller PRs concentrated around LSRA. This is part 1 of that.
For Arm64, this PR changes the typedef unsigned __int64 regMaskTP to `typedef
typedefstruct_regMaskTP
{
unsigned __int64 low;
} regMaskTP;
A version of PopCount and BitOperations has been added next to regMaskTP struct definition.
Most of the method implementation is pulled from #96196.
@ghostghost
added
the 
area-CodeGen-coreclr
CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
label
May 6, 2024
@kunalspathak
kunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

ContributorAuthor
@dotnet/jit-contrib
@dotnet-policy-service
dotnet-policy-serviceBot
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch

See info in area-owners.md if you want to be subscribed.
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
This is expected to be zero TP diff, so I will investigate why it is causing 2% regression. Possibly I missed updating something:
image
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
for windows/arm64 crossgen2 collection, here is the distribution. Will take a look
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AU_regMaskAll@@PEAVInterval@@PEAVRefPosition@@@Z : 7371109602 : NA : 24.12% : +4.3652%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@I@Z : 2298414560 : NA : 7.52% : +1.3611%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.02% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 976319605 : NA : 3.19% : +0.5782%
?mergeRegisterPreferences@Interval@@QEAAXU_regMaskAll@@@Z : 732180225 : NA : 2.40% : +0.4336%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 712437498 : NA : 2.33% : +0.4219%
?freeRegisters@LinearScan@@AEAAXU_regMaskAll@@@Z : 598599174 : NA : 1.96% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IU_regMaskAll@@@Z : 419647064 : NA : 1.37% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@@Z : 388348628 : NA : 1.27% : +0.2300%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 256572045 : +23.46% : 0.84% : +0.1519%
?gtGetRegMask@GenTree@@QEBA?AU_regMaskAll@@XZ : 247446771 : NA : 0.81% : +0.1465%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KU_regMaskAll@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.75% : +0.1357%
?addKillForRegs@LinearScan@@AEAAXU_regMaskAll@@I@Z : 103418880 : NA : 0.34% : +0.0612%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KU_regMaskAll@@@Z : 92569359 : NA : 0.30% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HU_regMaskAll@@@Z : 85318812 : NA : 0.28% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXU_regMaskAll@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.25% : +0.0446%
?emitEncodeCallGCregs@emitter@@CAXU_regMaskAll@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.24% : +0.0437%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 68804619 : NA : 0.23% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.18% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KU_regMaskAll@@1@Z : 51155804 : NA : 0.17% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.16% : +0.0298%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KU_regMaskAll@@3_N@Z : 46678609 : NA : 0.15% : +0.0276%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 46376391 : NA : 0.15% : +0.0275%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@U_regMaskAll@@PEAE@Z : 37957388 : NA : 0.12% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AU_regMaskAll@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.12% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.10% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.12% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.13% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.15% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.15% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.17% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.17% : -0.0305%
?buildUpperVectorRestoreRefPosition@LinearScan@@AEAAXPEAVInterval@@IPEAUGenTree@@_NI@Z : -62330666 : -100.00% : 0.20% : -0.0369%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.23% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.23% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.25% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.25% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.26% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.28% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.30% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.59% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.75% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.79% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.23% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.28% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 1.96% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.33% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.04% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.50% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.54% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 19.89% : -3.5995%

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@kunalspathak
kunalspathak
commented
May 9, 2024

Copy link


Copy Markdown

ContributorAuthor
The culprit was using PopCount() in genMaxOneBit() and genExactlyOneBit(). After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Base: 168859757414, Diff: 169865447753, +0.5956%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AUregMaskTP@@PEAVInterval@@PEAVRefPosition@@@Z : 6583187619 : NA : 22.90% : +3.8986%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@UregMaskTP@@I@Z : 1760063728 : NA : 6.12% : +1.0423%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.27% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 930438698 : NA : 3.24% : +0.5510%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 712437498 : NA : 2.48% : +0.4219%
?mergeRegisterPreferences@Interval@@QEAAXUregMaskTP@@@Z : 711153378 : NA : 2.47% : +0.4212%
?freeRegisters@LinearScan@@AEAAXUregMaskTP@@@Z : 598599174 : NA : 2.08% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IUregMaskTP@@@Z : 419548284 : NA : 1.46% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@UregMaskTP@@@Z : 388348628 : NA : 1.35% : +0.2300%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KUregMaskTP@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.80% : +0.1357%
?gtGetRegMask@GenTree@@QEBA?AUregMaskTP@@XZ : 191014321 : NA : 0.66% : +0.1131%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KUregMaskTP@@@Z : 92569359 : NA : 0.32% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HUregMaskTP@@@Z : 85318812 : NA : 0.30% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXUregMaskTP@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.26% : +0.0446%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 74404320 : +6.80% : 0.26% : +0.0441%
?emitEncodeCallGCregs@emitter@@CAXUregMaskTP@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.26% : +0.0437%
?addKillForRegs@LinearScan@@AEAAXUregMaskTP@@I@Z : 70669568 : NA : 0.25% : +0.0419%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 68804619 : NA : 0.24% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.19% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KUregMaskTP@@1@Z : 51155804 : NA : 0.18% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.18% : +0.0298%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 46376391 : NA : 0.16% : +0.0275%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KUregMaskTP@@3_N@Z : 45166929 : NA : 0.16% : +0.0267%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@UregMaskTP@@PEAE@Z : 37957388 : NA : 0.13% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AUregMaskTP@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.13% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.11% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.13% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.14% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.16% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.16% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.18% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.18% : -0.0305%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.24% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.25% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.26% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.26% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.28% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.30% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.32% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.63% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.80% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.84% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.30% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.36% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 2.08% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.48% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.23% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.79% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.89% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 21.15% : -3.5995%

@build-analysisbuild-analysisBot
mentioned this pull request
May 9, 2024

Closed

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+241
 to 
+244

 FORCEINLINE explicit operator unsigned int() const
 {
 return (unsigned int)low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This one we ought to remove as well.
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It is currently used only at one place. Ideally, all the *refRegs should be just gpr register set of size 4 bytes, but do not want to mix that change in this PR.
if (ig->igFlags & IGF_BYREF_REGS)
{
// Record the byref regs in front the of the instructions
*castto(id, unsigned*)++ = (unsigned)emitInitByrefRegs;
}
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated


Comment on lines

+984
 to 
+988

#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)BitScanForward(mask);
#else
 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
#endif
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It would be good to avoid these ifdefs by introducing some forwarding BitScanForward in the typedef unsigned __int64 regMaskTP case.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/lsra.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@jakobbotsch
jakobbotsch
commented
May 10, 2024

Copy link


Copy Markdown

Member
After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Yeah, seems to just be various MSVC regressions due to now having a struct instead of primitive type. Clang seems to do a little bit better. Not much we can do about that I think.
@jakobbotsch
jakobbotsch
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

Member
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
Alternatively we could move extra operations to live on some RegMaskOps type that operates on regMaskTP. That would probably allow all the client code to stay unified as well, even with regMaskTP typedeffed to a primitive.
@kunalspathak
kunalspathak
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

ContributorAuthor
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
I don't mind doing it and was advocate of similar idea back in #98258 because with that, in future, when we add APX support for Intel, enabling the "handling of 64 registers".
Edit: With that said, given that #98258 is already out for couple of months now and it is a critical work that is needed to make other progress for SVE, I would like to concentrate on enabling it with as minimal work as needed (just for arm64) and have it enable for other platforms as a follow up PRs once we complete the "predicate register" work.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+253
 to 
+256

 FORCEINLINE void setLow(uint64_t _low)
 {
 low = _low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I don't think we should have this one (can just assign the full regMaskTP instead)
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Feel free to include it in the follow up
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

(FWIW, it seems like bad encapsulation to have low accessible outside this class at all)
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I totally agree with you and was not a fan of having this in the last commit. May be I should just try assigning the whole regMaskTP.
@build-analysisbuild-analysisBot
mentioned this pull request
May 10, 2024

Closed

@kunalspathak
kunalspathak
commented
May 10, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-diffs
@azure-pipelines
azure-pipelinesBot
commented
May 10, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
image
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-replay
@azure-pipelines
azure-pipelinesBot
commented
May 11, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
merged commit fdc9c9d
into
dotnet:mainMay 11, 2024
@kunalspathak
kunalspathak
deleted the

more-than-64-part1

branch
May 11, 2024 06:02
Ruihan-Yin pushed a commit
to Ruihan-Yin/runtime
that referenced
this pull request
May 30, 2024
@kunalspathak@Ruihan-Yin
Handle more than 64 registers - Part 1 (dotnet#101950)
20a6043
* Convert regMaskTP for ARM64 to struct with single field
* Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()
* minor fix
* review feedback
* fix the TP regression from 1.5% -> 0.5%
* Pass by value
* jit format
* review feedback
* Remove FORCEINLINE
* Remove setLow()
@github-actionsgithub-actionsBot
locked and limited conversation to collaborators
Jun 10, 2024
Sign up for freeto subscribe to this conversation on GitHub.
Already have an account?
Sign in.


Reviewers

@jakobbotschjakobbotschjakobbotsch approved these changes

Assignees

@kunalspathakkunalspathak

Labels

area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

Projects


None yet


Milestone


No milestone


Development

Successfully merging this pull request may close these issues.

2 participants

@kunalspathak@jakobbotsch

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Remove or un-stick sticky/fixed headers that block content\n(function() {\n function unstick() {\n document.querySelectorAll('header, nav, [role=\"banner\"], .header, .navbar, .sticky, .fixed-top, [style*=\"position: fixed\"], [style*=\"position:sticky\"]').forEach(function(el) {\n if (el.style.position === 'fixed' || el.style.position === 'sticky' || \n getComputedStyle(el).position === 'fixed' || getComputedStyle(el).position === 'sticky') {\n el.style.position = 'static';\n el.style.top = 'auto';\n el.style.zIndex = 'auto';\n }\n });\n }\n \n unstick();\n \n var observer = new MutationObserver(unstick);\n observer.observe(document.body, { childList: true, subtree: true, attributes: true, attributeFilter: ['style', 'class'] });\n})();", "Kill Sticky Headers");
}
} catch(__e) { console.warn('[Userscript:Kill Sticky Headers]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
Handle more than 64 registers - Part 1 - #101950
Merged
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
May 11, 2024
Merged
Handle more than 64 registers - Part 1#101950
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
Conversation
@kunalspathak
@kunalspathakkunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
The general feedback for #98258 was to come up with smaller PRs concentrated around LSRA. This is part 1 of that.
For Arm64, this PR changes the typedef unsigned __int64 regMaskTP to `typedef
typedefstruct_regMaskTP
{
unsigned __int64 low;
} regMaskTP;
A version of PopCount and BitOperations has been added next to regMaskTP struct definition.
Most of the method implementation is pulled from #96196.
@ghostghost
added
the 
area-CodeGen-coreclr
CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
label
May 6, 2024
@kunalspathak
kunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

ContributorAuthor
@dotnet/jit-contrib
@dotnet-policy-service
dotnet-policy-serviceBot
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch

See info in area-owners.md if you want to be subscribed.
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
This is expected to be zero TP diff, so I will investigate why it is causing 2% regression. Possibly I missed updating something:
image
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
for windows/arm64 crossgen2 collection, here is the distribution. Will take a look
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AU_regMaskAll@@PEAVInterval@@PEAVRefPosition@@@Z : 7371109602 : NA : 24.12% : +4.3652%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@I@Z : 2298414560 : NA : 7.52% : +1.3611%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.02% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 976319605 : NA : 3.19% : +0.5782%
?mergeRegisterPreferences@Interval@@QEAAXU_regMaskAll@@@Z : 732180225 : NA : 2.40% : +0.4336%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 712437498 : NA : 2.33% : +0.4219%
?freeRegisters@LinearScan@@AEAAXU_regMaskAll@@@Z : 598599174 : NA : 1.96% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IU_regMaskAll@@@Z : 419647064 : NA : 1.37% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@@Z : 388348628 : NA : 1.27% : +0.2300%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 256572045 : +23.46% : 0.84% : +0.1519%
?gtGetRegMask@GenTree@@QEBA?AU_regMaskAll@@XZ : 247446771 : NA : 0.81% : +0.1465%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KU_regMaskAll@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.75% : +0.1357%
?addKillForRegs@LinearScan@@AEAAXU_regMaskAll@@I@Z : 103418880 : NA : 0.34% : +0.0612%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KU_regMaskAll@@@Z : 92569359 : NA : 0.30% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HU_regMaskAll@@@Z : 85318812 : NA : 0.28% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXU_regMaskAll@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.25% : +0.0446%
?emitEncodeCallGCregs@emitter@@CAXU_regMaskAll@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.24% : +0.0437%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 68804619 : NA : 0.23% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.18% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KU_regMaskAll@@1@Z : 51155804 : NA : 0.17% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.16% : +0.0298%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KU_regMaskAll@@3_N@Z : 46678609 : NA : 0.15% : +0.0276%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 46376391 : NA : 0.15% : +0.0275%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@U_regMaskAll@@PEAE@Z : 37957388 : NA : 0.12% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AU_regMaskAll@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.12% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.10% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.12% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.13% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.15% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.15% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.17% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.17% : -0.0305%
?buildUpperVectorRestoreRefPosition@LinearScan@@AEAAXPEAVInterval@@IPEAUGenTree@@_NI@Z : -62330666 : -100.00% : 0.20% : -0.0369%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.23% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.23% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.25% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.25% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.26% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.28% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.30% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.59% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.75% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.79% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.23% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.28% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 1.96% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.33% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.04% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.50% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.54% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 19.89% : -3.5995%

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@kunalspathak
kunalspathak
commented
May 9, 2024

Copy link


Copy Markdown

ContributorAuthor
The culprit was using PopCount() in genMaxOneBit() and genExactlyOneBit(). After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Base: 168859757414, Diff: 169865447753, +0.5956%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AUregMaskTP@@PEAVInterval@@PEAVRefPosition@@@Z : 6583187619 : NA : 22.90% : +3.8986%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@UregMaskTP@@I@Z : 1760063728 : NA : 6.12% : +1.0423%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.27% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 930438698 : NA : 3.24% : +0.5510%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 712437498 : NA : 2.48% : +0.4219%
?mergeRegisterPreferences@Interval@@QEAAXUregMaskTP@@@Z : 711153378 : NA : 2.47% : +0.4212%
?freeRegisters@LinearScan@@AEAAXUregMaskTP@@@Z : 598599174 : NA : 2.08% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IUregMaskTP@@@Z : 419548284 : NA : 1.46% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@UregMaskTP@@@Z : 388348628 : NA : 1.35% : +0.2300%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KUregMaskTP@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.80% : +0.1357%
?gtGetRegMask@GenTree@@QEBA?AUregMaskTP@@XZ : 191014321 : NA : 0.66% : +0.1131%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KUregMaskTP@@@Z : 92569359 : NA : 0.32% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HUregMaskTP@@@Z : 85318812 : NA : 0.30% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXUregMaskTP@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.26% : +0.0446%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 74404320 : +6.80% : 0.26% : +0.0441%
?emitEncodeCallGCregs@emitter@@CAXUregMaskTP@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.26% : +0.0437%
?addKillForRegs@LinearScan@@AEAAXUregMaskTP@@I@Z : 70669568 : NA : 0.25% : +0.0419%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 68804619 : NA : 0.24% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.19% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KUregMaskTP@@1@Z : 51155804 : NA : 0.18% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.18% : +0.0298%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 46376391 : NA : 0.16% : +0.0275%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KUregMaskTP@@3_N@Z : 45166929 : NA : 0.16% : +0.0267%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@UregMaskTP@@PEAE@Z : 37957388 : NA : 0.13% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AUregMaskTP@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.13% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.11% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.13% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.14% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.16% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.16% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.18% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.18% : -0.0305%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.24% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.25% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.26% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.26% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.28% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.30% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.32% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.63% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.80% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.84% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.30% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.36% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 2.08% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.48% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.23% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.79% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.89% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 21.15% : -3.5995%

@build-analysisbuild-analysisBot
mentioned this pull request
May 9, 2024

Closed

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+241
 to 
+244

 FORCEINLINE explicit operator unsigned int() const
 {
 return (unsigned int)low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This one we ought to remove as well.
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It is currently used only at one place. Ideally, all the *refRegs should be just gpr register set of size 4 bytes, but do not want to mix that change in this PR.
if (ig->igFlags & IGF_BYREF_REGS)
{
// Record the byref regs in front the of the instructions
*castto(id, unsigned*)++ = (unsigned)emitInitByrefRegs;
}
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated


Comment on lines

+984
 to 
+988

#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)BitScanForward(mask);
#else
 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
#endif
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It would be good to avoid these ifdefs by introducing some forwarding BitScanForward in the typedef unsigned __int64 regMaskTP case.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/lsra.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@jakobbotsch
jakobbotsch
commented
May 10, 2024

Copy link


Copy Markdown

Member
After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Yeah, seems to just be various MSVC regressions due to now having a struct instead of primitive type. Clang seems to do a little bit better. Not much we can do about that I think.
@jakobbotsch
jakobbotsch
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

Member
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
Alternatively we could move extra operations to live on some RegMaskOps type that operates on regMaskTP. That would probably allow all the client code to stay unified as well, even with regMaskTP typedeffed to a primitive.
@kunalspathak
kunalspathak
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

ContributorAuthor
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
I don't mind doing it and was advocate of similar idea back in #98258 because with that, in future, when we add APX support for Intel, enabling the "handling of 64 registers".
Edit: With that said, given that #98258 is already out for couple of months now and it is a critical work that is needed to make other progress for SVE, I would like to concentrate on enabling it with as minimal work as needed (just for arm64) and have it enable for other platforms as a follow up PRs once we complete the "predicate register" work.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+253
 to 
+256

 FORCEINLINE void setLow(uint64_t _low)
 {
 low = _low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I don't think we should have this one (can just assign the full regMaskTP instead)
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Feel free to include it in the follow up
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

(FWIW, it seems like bad encapsulation to have low accessible outside this class at all)
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I totally agree with you and was not a fan of having this in the last commit. May be I should just try assigning the whole regMaskTP.
@build-analysisbuild-analysisBot
mentioned this pull request
May 10, 2024

Closed

@kunalspathak
kunalspathak
commented
May 10, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-diffs
@azure-pipelines
azure-pipelinesBot
commented
May 10, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
image
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-replay
@azure-pipelines
azure-pipelinesBot
commented
May 11, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
merged commit fdc9c9d
into
dotnet:mainMay 11, 2024
@kunalspathak
kunalspathak
deleted the

more-than-64-part1

branch
May 11, 2024 06:02
Ruihan-Yin pushed a commit
to Ruihan-Yin/runtime
that referenced
this pull request
May 30, 2024
@kunalspathak@Ruihan-Yin
Handle more than 64 registers - Part 1 (dotnet#101950)
20a6043
* Convert regMaskTP for ARM64 to struct with single field
* Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()
* minor fix
* review feedback
* fix the TP regression from 1.5% -> 0.5%
* Pass by value
* jit format
* review feedback
* Remove FORCEINLINE
* Remove setLow()
@github-actionsgithub-actionsBot
locked and limited conversation to collaborators
Jun 10, 2024
Sign up for freeto subscribe to this conversation on GitHub.
Already have an account?
Sign in.


Reviewers

@jakobbotschjakobbotschjakobbotsch approved these changes

Assignees

@kunalspathakkunalspathak

Labels

area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

Projects


None yet


Milestone


No milestone


Development

Successfully merging this pull request may close these issues.

2 participants

@kunalspathak@jakobbotsch

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Universal Dark Mode - works on any site\n(function() {\n var enabled = true;\n \n function applyDarkMode() {\n if (!enabled) return;\n \n // Create style element if it doesn't exist\n var style = document.getElementById('universal-dark-mode-style');\n if (!style) {\n style = document.createElement('style');\n style.id = 'universal-dark-mode-style';\n document.head.appendChild(style);\n }\n \n // Dark mode CSS - inverts colors but preserves images/video\n style.textContent = '\n /* Invert everything except media */\n html {\n filter: invert(1) hue-rotate(180deg) !important;\n background: #1a1a2e !important;\n }\n \n /* Restore images, videos, iframes, canvas */\n img, video, iframe, canvas, svg, picture, [style*=\"background-image\"] {\n filter: invert(1) hue-rotate(180deg) !important;\n }\n \n /* Preserve specific elements that should not be inverted */\n .no-dark-mode, .no-dark-mode *,\n [data-theme=\"light\"], [data-theme=\"light\"],\n .ace_editor, .ace_editor *,\n .CodeMirror, .CodeMirror *,\n .monaco-editor, .monaco-editor *,\n .markdown-body pre, .markdown-body pre *,\n .highlight, .highlight *,\n pre code, pre code * {\n filter: none !important;\n }\n \n /* Fix common UI elements */\n .modal, .popup, .dropdown-menu, .tooltip, .popover {\n filter: invert(1) hue-rotate(180deg) !important;\n background: #2d2d44 !important;\n border-color: #444 !important;\n }\n \n /* Scrollbars */\n ::-webkit-scrollbar { background: #1a1a2e !important; }\n ::-webkit-scrollbar-thumb { background: #444 !important; }\n ::-webkit-scrollbar-thumb:hover { background: #555 !important; }\n \n /* Selection */\n ::selection { background: #4ecdc4 !important; color: #1a1a2e !important; }\n ::-moz-selection { background: #4ecdc4 !important; color: #1a1a2e !important; }\n ';\n }\n \n function removeDarkMode() {\n var style = document.getElementById('universal-dark-mode-style');\n if (style) style.remove();\n }\n \n // Toggle with Alt+Shift+D\n document.addEventListener('keydown', function(e) {\n if (e.altKey && e.shiftKey && e.key === 'D') {\n e.preventDefault();\n enabled = !enabled;\n if (enabled) {\n applyDarkMode();\n console.log('[Universal Dark Mode] Enabled');\n } else {\n removeDarkMode();\n console.log('[Universal Dark Mode] Disabled');\n }\n }\n });\n \n // Apply on load\n applyDarkMode();\n \n // Re-apply on dynamic content\n var observer = new MutationObserver(function(mutations) {\n if (enabled && !document.getElementById('universal-dark-mode-style')) {\n applyDarkMode();\n }\n });\n observer.observe(document.head, { childList: true });\n \n console.log('[Universal Dark Mode] Loaded - Press Alt+Shift+D to toggle');\n})();", "Universal Dark Mode");
}
} catch(__e) { console.warn('[Userscript:Universal Dark Mode]', __e); }
})();
})();

Skip to content
Handle more than 64 registers - Part 1 - #101950
Merged
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
May 11, 2024
Merged
Handle more than 64 registers - Part 1#101950
kunalspathak merged 10 commits into
dotnet:mainfrom 
kunalspathak:more-than-64-part1
Conversation
@kunalspathak
@kunalspathakkunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
The general feedback for #98258 was to come up with smaller PRs concentrated around LSRA. This is part 1 of that.
For Arm64, this PR changes the typedef unsigned __int64 regMaskTP to `typedef
typedefstruct_regMaskTP
{
unsigned __int64 low;
} regMaskTP;
A version of PopCount and BitOperations has been added next to regMaskTP struct definition.
Most of the method implementation is pulled from #96196.
@ghostghost
added
the 
area-CodeGen-coreclr
CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
label
May 6, 2024
@kunalspathak
kunalspathak
commented
May 6, 2024

Copy link


Copy Markdown

ContributorAuthor
@dotnet/jit-contrib
@dotnet-policy-service
dotnet-policy-serviceBot
commented
May 6, 2024

Copy link


Copy Markdown

Contributor
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch

See info in area-owners.md if you want to be subscribed.
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
This is expected to be zero TP diff, so I will investigate why it is causing 2% regression. Possibly I missed updating something:
image
@kunalspathak
kunalspathak
commented
May 7, 2024

Copy link


Copy Markdown

ContributorAuthor
for windows/arm64 crossgen2 collection, here is the distribution. Will take a look
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AU_regMaskAll@@PEAVInterval@@PEAVRefPosition@@@Z : 7371109602 : NA : 24.12% : +4.3652%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@I@Z : 2298414560 : NA : 7.52% : +1.3611%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.02% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 976319605 : NA : 3.19% : +0.5782%
?mergeRegisterPreferences@Interval@@QEAAXU_regMaskAll@@@Z : 732180225 : NA : 2.40% : +0.4336%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@U_regMaskAll@@H@Z : 712437498 : NA : 2.33% : +0.4219%
?freeRegisters@LinearScan@@AEAAXU_regMaskAll@@@Z : 598599174 : NA : 1.96% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IU_regMaskAll@@@Z : 419647064 : NA : 1.37% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@U_regMaskAll@@@Z : 388348628 : NA : 1.27% : +0.2300%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 256572045 : +23.46% : 0.84% : +0.1519%
?gtGetRegMask@GenTree@@QEBA?AU_regMaskAll@@XZ : 247446771 : NA : 0.81% : +0.1465%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KU_regMaskAll@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.75% : +0.1357%
?addKillForRegs@LinearScan@@AEAAXU_regMaskAll@@I@Z : 103418880 : NA : 0.34% : +0.0612%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KU_regMaskAll@@@Z : 92569359 : NA : 0.30% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HU_regMaskAll@@@Z : 85318812 : NA : 0.28% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXU_regMaskAll@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.25% : +0.0446%
?emitEncodeCallGCregs@emitter@@CAXU_regMaskAll@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.24% : +0.0437%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 68804619 : NA : 0.23% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.18% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KU_regMaskAll@@1@Z : 51155804 : NA : 0.17% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.16% : +0.0298%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KU_regMaskAll@@3_N@Z : 46678609 : NA : 0.15% : +0.0276%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@U_regMaskAll@@@Z : 46376391 : NA : 0.15% : +0.0275%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@U_regMaskAll@@PEAE@Z : 37957388 : NA : 0.12% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AU_regMaskAll@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.12% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.10% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.12% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.13% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.15% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.15% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.17% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.17% : -0.0305%
?buildUpperVectorRestoreRefPosition@LinearScan@@AEAAXPEAVInterval@@IPEAUGenTree@@_NI@Z : -62330666 : -100.00% : 0.20% : -0.0369%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.23% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.23% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.25% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.25% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.26% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.28% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.30% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.59% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.75% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.79% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.23% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.28% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 1.96% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.33% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.04% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.50% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.54% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 19.89% : -3.5995%

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 7, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@kunalspathak
kunalspathak
commented
May 9, 2024

Copy link


Copy Markdown

ContributorAuthor
The culprit was using PopCount() in genMaxOneBit() and genExactlyOneBit(). After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Base: 168859757414, Diff: 169865447753, +0.5956%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA?AUregMaskTP@@PEAVInterval@@PEAVRefPosition@@@Z : 6583187619 : NA : 22.90% : +3.8986%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@UregMaskTP@@I@Z : 1760063728 : NA : 6.12% : +1.0423%
?processKills@LinearScan@@AEAAXPEAVRefPosition@@@Z : 1228183017 : NA : 4.27% : +0.7273%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 930438698 : NA : 3.24% : +0.5510%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@UregMaskTP@@H@Z : 712437498 : NA : 2.48% : +0.4219%
?mergeRegisterPreferences@Interval@@QEAAXUregMaskTP@@@Z : 711153378 : NA : 2.47% : +0.4212%
?freeRegisters@LinearScan@@AEAAXUregMaskTP@@@Z : 598599174 : NA : 2.08% : +0.3545%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@IUregMaskTP@@@Z : 419548284 : NA : 1.46% : +0.2485%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@UregMaskTP@@@Z : 388348628 : NA : 1.35% : +0.2300%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_KUregMaskTP@@6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : 229060387 : NA : 0.80% : +0.1357%
?gtGetRegMask@GenTree@@QEBA?AUregMaskTP@@XZ : 191014321 : NA : 0.66% : +0.1131%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_KUregMaskTP@@@Z : 92569359 : NA : 0.32% : +0.0548%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@HUregMaskTP@@@Z : 85318812 : NA : 0.30% : +0.0505%
?genBuildRegPairsStack@CodeGen@@KAXUregMaskTP@@PEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : 75277373 : NA : 0.26% : +0.0446%
?associateRefPosWithInterval@LinearScan@@AEAAXPEAVRefPosition@@@Z : 74404320 : +6.80% : 0.26% : +0.0441%
?emitEncodeCallGCregs@emitter@@CAXUregMaskTP@@PEAUinstrDesc@1@@Z : 73781054 : NA : 0.26% : +0.0437%
?addKillForRegs@LinearScan@@AEAAXUregMaskTP@@I@Z : 70669568 : NA : 0.25% : +0.0419%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 68804619 : NA : 0.24% : +0.0407%
?BuildNode@LinearScan@@AEAAHPEAUGenTree@@@Z : 54306503 : +4.65% : 0.19% : +0.0322%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_KUregMaskTP@@1@Z : 51155804 : NA : 0.18% : +0.0303%
?assignPhysReg@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : 50356789 : +10.96% : 0.18% : +0.0298%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@UregMaskTP@@@Z : 46376391 : NA : 0.16% : +0.0275%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_KUregMaskTP@@3_N@Z : 45166929 : NA : 0.16% : +0.0267%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@UregMaskTP@@PEAE@Z : 37957388 : NA : 0.13% : +0.0225%
?getMatchingConstants@LinearScan@@AEAA?AUregMaskTP@@U2@PEAVInterval@@PEAVRefPosition@@@Z : 36052458 : NA : 0.13% : +0.0214%
??$processBlockEndAllocation@$00@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -31931508 : -99.99% : 0.11% : -0.0189%
?emitGCregDeadSet@emitter@@QEAAXW4GCtype@@_KPEAE@Z : -37957388 : -100.00% : 0.13% : -0.0225%
?getMatchingConstants@LinearScan@@AEAA_K_KPEAVInterval@@PEAVRefPosition@@@Z : -40340140 : -100.00% : 0.14% : -0.0239%
?emitCreatePlaceholderIG@emitter@@QEAAXW4insGroupPlaceholderType@@PEAUBasicBlock@@AEBQEA_K_K3_N@Z : -45166929 : -100.00% : 0.16% : -0.0267%
?BuildAddrUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -46376391 : -100.00% : 0.16% : -0.0275%
?emitAddLabel@emitter@@AEAAPEAXAEBQEA_K_K1@Z : -51155804 : -100.00% : 0.18% : -0.0303%
?updateAssignedInterval@LinearScan@@AEAAXPEAVRegRecord@@PEAVInterval@@@Z : -51531940 : -7.61% : 0.18% : -0.0305%
?BuildOperandUses@LinearScan@@AEAAHPEAUGenTree@@_K@Z : -68804619 : -100.00% : 0.24% : -0.0407%
?addKillForRegs@LinearScan@@AEAAX_KI@Z : -70669568 : -100.00% : 0.25% : -0.0419%
?emitEncodeCallGCregs@emitter@@CAX_KPEAUinstrDesc@1@@Z : -74971071 : -100.00% : 0.26% : -0.0444%
?genBuildRegPairsStack@CodeGen@@KAX_KPEAV?$ArrayStack@URegPair@CodeGen@@@@@Z : -75003566 : -100.00% : 0.26% : -0.0444%
?processBlockStartLocations@LinearScan@@AEAAXPEAUBasicBlock@@@Z : -80628252 : -5.11% : 0.28% : -0.0477%
?BuildDefs@LinearScan@@AEAAXPEAUGenTree@@H_K@Z : -85318812 : -100.00% : 0.30% : -0.0505%
?resolveEdge@LinearScan@@QEAAXPEAUBasicBlock@@0W4ResolveType@1@AEBQEA_K_K@Z : -91554003 : -100.00% : 0.32% : -0.0542%
?gtGetRegMask@GenTree@@QEBA_KXZ : -181640807 : -100.00% : 0.63% : -0.1076%
?emitIns_Call@emitter@@QEAAXW4EmitCallType@1@PEAUCORINFO_METHOD_STRUCT_@@PEAX_JW4emitAttr@@4AEBQEA_K_K6AEBVDebugInfo@@W4_regNumber_enum@@8I3_N@Z : -229060387 : -100.00% : 0.80% : -0.1357%
?updateRegisterPreferences@Interval@@QEAAX_K@Z : -240144624 : -100.00% : 0.84% : -0.1422%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@W4_regNumber_enum@@IW4RefType@@PEAUGenTree@@_K@Z : -374957296 : -100.00% : 1.30% : -0.2221%
?buildKillPositionsForNode@LinearScan@@AEAA_NPEAUGenTree@@I_K@Z : -390519208 : -100.00% : 1.36% : -0.2313%
?freeRegisters@LinearScan@@AEAAX_K@Z : -598599174 : -100.00% : 2.08% : -0.3545%
?BuildDef@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -712437498 : -100.00% : 2.48% : -0.4219%
?BuildUse@LinearScan@@AEAAPEAVRefPosition@@PEAUGenTree@@_KH@Z : -927590191 : -100.00% : 3.23% : -0.5493%
??$allocateRegisters@$0A@@LinearScan@@QEAAXXZ : -1375837725 : -19.43% : 4.79% : -0.8148%
?newRefPosition@LinearScan@@AEAAPEAVRefPosition@@PEAVInterval@@IW4RefType@@PEAUGenTree@@_KI@Z : -1693247150 : -100.00% : 5.89% : -1.0028%
??$select@$0A@@RegisterSelection@LinearScan@@QEAA_KPEAVInterval@@PEAVRefPosition@@@Z : -6078036133 : -100.00% : 21.15% : -3.5995%

@build-analysisbuild-analysisBot
mentioned this pull request
May 9, 2024

Closed

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+241
 to 
+244

 FORCEINLINE explicit operator unsigned int() const
 {
 return (unsigned int)low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This one we ought to remove as well.
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It is currently used only at one place. Ideally, all the *refRegs should be just gpr register set of size 4 bytes, but do not want to mix that change in this PR.
if (ig->igFlags & IGF_BYREF_REGS)
{
// Record the byref regs in front the of the instructions
*castto(id, unsigned*)++ = (unsigned)emitInitByrefRegs;
}
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/compiler.hpp
Outdated


Comment on lines

+984
 to 
+988

#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)BitScanForward(mask);
#else
 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
#endif
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It would be good to avoid these ifdefs by introducing some forwarding BitScanForward in the typedef unsigned __int64 regMaskTP case.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/lsra.h
Outdated

jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated

@jakobbotsch
jakobbotsch
commented
May 10, 2024

Copy link


Copy Markdown

Member
After fixing it, the regression drops to 0.5%. The remaining regression is just scattered around because of various factors and is not related to any specific pattern.
Yeah, seems to just be various MSVC regressions due to now having a struct instead of primitive type. Clang seems to do a little bit better. Not much we can do about that I think.
@jakobbotsch
jakobbotsch
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

Member
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
Alternatively we could move extra operations to live on some RegMaskOps type that operates on regMaskTP. That would probably allow all the client code to stay unified as well, even with regMaskTP typedeffed to a primitive.
@kunalspathak
kunalspathak
commented
May 10, 2024•

edited

Loading

Copy link


Copy Markdown

ContributorAuthor
We might consider switching regMaskTP to a struct everywhere instead of having it as a primitive, to have it unified everywhere. I would personally prefer it, even if it causes MSVC to pessimize codegen slightly. Thoughts @dotnet/jit-contrib?
I don't mind doing it and was advocate of similar idea back in #98258 because with that, in future, when we add APX support for Intel, enabling the "handling of 64 registers".
Edit: With that said, given that #98258 is already out for couple of months now and it is a critical work that is needed to make other progress for SVE, I would like to concentrate on enabling it with as minimal work as needed (just for arm64) and have it enable for other platforms as a follow up PRs once we complete the "predicate register" work.
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
jakobbotsch
jakobbotsch
reviewed
May 10, 2024
View reviewed changes
Comment threadsrc/coreclr/jit/target.h
Outdated


Comment on lines

+253
 to 
+256

 FORCEINLINE void setLow(uint64_t _low)
 {
 low = _low;
 }
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I don't think we should have this one (can just assign the full regMaskTP instead)
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Feel free to include it in the follow up
@jakobbotschjakobbotschMay 10, 2024

Copy link


Copy Markdown

Member
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

(FWIW, it seems like bad encapsulation to have low accessible outside this class at all)
@kunalspathakkunalspathakMay 10, 2024

Copy link


Copy Markdown

ContributorAuthor
Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I totally agree with you and was not a fan of having this in the last commit. May be I should just try assigning the whole regMaskTP.
@build-analysisbuild-analysisBot
mentioned this pull request
May 10, 2024

Closed

@kunalspathak
kunalspathak
commented
May 10, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-diffs
@azure-pipelines
azure-pipelinesBot
commented
May 10, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
image
@kunalspathak
kunalspathak
commented
May 11, 2024

Copy link


Copy Markdown

ContributorAuthor
/azp run runtime-coreclr superpmi-replay
@azure-pipelines
azure-pipelinesBot
commented
May 11, 2024

Copy link


Copy Markdown


Azure Pipelines successfully started running 1 pipeline(s).
@kunalspathak
kunalspathak
merged commit fdc9c9d
into
dotnet:mainMay 11, 2024
@kunalspathak
kunalspathak
deleted the

more-than-64-part1

branch
May 11, 2024 06:02
Ruihan-Yin pushed a commit
to Ruihan-Yin/runtime
that referenced
this pull request
May 30, 2024
@kunalspathak@Ruihan-Yin
Handle more than 64 registers - Part 1 (dotnet#101950)
20a6043
* Convert regMaskTP for ARM64 to struct with single field
* Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()
* minor fix
* review feedback
* fix the TP regression from 1.5% -> 0.5%
* Pass by value
* jit format
* review feedback
* Remove FORCEINLINE
* Remove setLow()
@github-actionsgithub-actionsBot
locked and limited conversation to collaborators
Jun 10, 2024
Sign up for freeto subscribe to this conversation on GitHub.
Already have an account?
Sign in.


Reviewers

@jakobbotschjakobbotschjakobbotsch approved these changes

Assignees

@kunalspathakkunalspathak

Labels

area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

Projects


None yet


Milestone


No milestone


Development

Successfully merging this pull request may close these issues.

2 participants

@kunalspathak@jakobbotsch