Handle more than 64 registers - Part 1#101950

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Merged
kunalspathak merged 10 commits into from
May 11, 2024
Merged

Handle more than 64 registers - Part 1 #101950

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f436712
Convert regMaskTP for ARM64 to struct with single field
kunalspathak May 6, 2024
8ff7508
Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()
kunalspathak May 6, 2024
7ac4137
minor fix
kunalspathak May 6, 2024
0144cb0
review feedback
kunalspathak May 8, 2024
81b26c6
fix the TP regression from 1.5% -> 0.5%
kunalspathak May 8, 2024
261ab5d
Pass by value
kunalspathak May 8, 2024
639290c
jit format
kunalspathak May 9, 2024
28b457d
review feedback
kunalspathak May 10, 2024
0a0e61d
Remove FORCEINLINE
kunalspathak May 10, 2024
8fdbf3f
Remove setLow()
kunalspathak May 10, 2024
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9 changes: 4 additions & 5 deletions src/coreclr/jit/codegencommon.cpp
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Original file line numberDiff line numberDiff line change
Expand Up@@ -3829,9 +3829,9 @@ void CodeGen::genZeroInitFltRegs(const regMaskTP& initFltRegs, const regMaskTP&

// Iterate through float/double registers and initialize them to 0 or
// copy from already initialized register of the same type.
regMaskTP regMask = genRegMask(REG_FP_FIRST);
for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg), regMask <<= 1)
for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg))
{
regMaskTP regMask = genRegMask(reg);
if (regMask & initFltRegs)
{
// Do we have a float register already set to 0?
Expand DownExpand Up@@ -5732,10 +5732,9 @@ void CodeGen::genFnProlog()

if (initRegs)
{
regMaskTP regMask = 0x1;

for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg), regMask <<= 1)
for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg))
{
regMaskTP regMask = genRegMask(reg);
if (regMask & initRegs)
{
// Check if we have already zeroed this register
Expand Down
64 changes: 61 additions & 3 deletions src/coreclr/jit/compiler.hpp
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Original file line numberDiff line numberDiff line change
Expand Up@@ -99,6 +99,33 @@ inline bool genExactlyOneBit(T value)
return ((value != 0) && genMaxOneBit(value));
}

#ifdef TARGET_ARM64
inline regMaskTP genFindLowestBit(regMaskTP value)
{
return regMaskTP(genFindLowestBit(value.getLow()));
}

/*****************************************************************************
*
* Return true if the given value has exactly zero or one bits set.
*/

inline bool genMaxOneBit(regMaskTP value)
{
return genMaxOneBit(value.getLow());
}

/*****************************************************************************
*
* Return true if the given value has exactly one bit set.
*/

inline bool genExactlyOneBit(regMaskTP value)
{
return genExactlyOneBit(value.getLow());
}
#endif

/*****************************************************************************
*
* Given a value that has exactly one bit set, return the position of that
Expand DownExpand Up@@ -147,6 +174,13 @@ inline unsigned genCountBits(uint64_t bits)
return BitOperations::PopCount(bits);
}

#ifdef TARGET_ARM64
inline unsigned genCountBits(regMaskTP mask)
{
return BitOperations::PopCount(mask.getLow());
}
#endif

/*****************************************************************************
*
* A rather simple routine that counts the number of bits in a given number.
Expand DownExpand Up@@ -914,11 +948,18 @@ inline regNumber genRegNumFromMask(regMaskTP mask)

/* Convert the mask to a register number */

regNumber regNum = (regNumber)genLog2(mask);
#ifdef TARGET_ARM64
regNumber regNum = (regNumber)genLog2(mask.getLow());

/* Make sure we got it right */
assert(genRegMask(regNum) == mask.getLow());

#else
regNumber regNum = (regNumber)genLog2(mask);

/* Make sure we got it right */
assert(genRegMask(regNum) == mask);
#endif

return regNum;
}
Expand All@@ -940,7 +981,8 @@ inline regNumber genFirstRegNumFromMaskAndToggle(regMaskTP& mask)

/* Convert the mask to a register number */

regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
regNumber regNum = (regNumber)BitScanForward(mask);

mask ^= genRegMask(regNum);

return regNum;
Expand All@@ -962,7 +1004,7 @@ inline regNumber genFirstRegNumFromMask(regMaskTP mask)

/* Convert the mask to a register number */

regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
regNumber regNum = (regNumber)BitScanForward(mask);

return regNum;
}
Expand DownExpand Up@@ -4463,30 +4505,46 @@ inline void* operator new[](size_t sz, Compiler* compiler, CompMemKind cmk)

inline void printRegMask(regMaskTP mask)
{
#ifdef TARGET_ARM64
printf(REG_MASK_ALL_FMT, mask.getLow());
#else
printf(REG_MASK_ALL_FMT, mask);
#endif
}

inline char* regMaskToString(regMaskTP mask, Compiler* context)
{
const size_t cchRegMask = 24;
char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask.getLow());
#else
sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask);
#endif

return regmask;
}

inline void printRegMaskInt(regMaskTP mask)
{
#ifdef TARGET_ARM64
printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif
}

inline char* regMaskIntToString(regMaskTP mask, Compiler* context)
{
const size_t cchRegMask = 24;
char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif

return regmask;
}
Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/jit/emit.cpp
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Original file line numberDiff line numberDiff line change
Expand Up@@ -3470,7 +3470,7 @@ void emitter::emitDispRegSet(regMaskTP regs)
continue;
}

regs -= curReg;
regs ^= curReg;

if (sp)
{
Expand DownExpand Up@@ -3828,8 +3828,8 @@ void emitter::emitDispGCRegDelta(const char* title, regMaskTP prevRegs, regMaskT
{
emitDispGCDeltaTitle(title);
regMaskTP sameRegs = prevRegs & curRegs;
regMaskTP removedRegs = prevRegs - sameRegs;
regMaskTP addedRegs = curRegs - sameRegs;
regMaskTP removedRegs = prevRegs ^ sameRegs;
regMaskTP addedRegs = curRegs ^ sameRegs;
if (removedRegs != RBM_NONE)
{
printf(" -");
Expand DownExpand Up@@ -8920,7 +8920,7 @@ void emitter::emitUpdateLiveGCregs(GCtype gcType, regMaskTP regs, BYTE* addr)
emitGCregDeadUpd(reg, addr);
}

chg -= bit;
chg ^= bit;
} while (chg);

assert(emitThisXXrefRegs == regs);
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/jit/gcencode.cpp
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Expand Up@@ -4667,7 +4667,7 @@ void GCInfo::gcInfoRecordGCRegStateChange(GcInfoEncoder* gcInfoEncoder,
}

// Turn the bit we've just generated off and continue.
regMask -= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
regMask ^= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
}
}

Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/jit/lsra.cpp
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Expand Up@@ -13609,7 +13609,7 @@ regMaskTP LinearScan::RegisterSelection::select(Interval* current
&overallLimitCandidates);
assert(limitConsecutiveResult != RBM_NONE);

unsigned startRegister = BitOperations::BitScanForward(limitConsecutiveResult);
unsigned startRegister = BitScanForward(limitConsecutiveResult);

regMaskTP registersNeededMask = (1ULL << refPosition->regCount) - 1;
candidates |= (registersNeededMask << startRegister);
Expand Down
4 changes: 2 additions & 2 deletions src/coreclr/jit/lsra.h
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Expand Up@@ -794,8 +794,8 @@ class LinearScan : public LinearScanInterface
static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R3 | RBM_R4 | RBM_R5);
static const regMaskTP LsraLimitSmallFPSet = (RBM_F0 | RBM_F1 | RBM_F2 | RBM_F16 | RBM_F17);
#elif defined(TARGET_ARM64)
static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
static const regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
static constexpr regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
static constexpr regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
#elif defined(TARGET_X86)
static const regMaskTP LsraLimitSmallIntSet = (RBM_EAX | RBM_ECX | RBM_EDI);
static const regMaskTP LsraLimitSmallFPSet = (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM6 | RBM_XMM7);
Expand Down
10 changes: 5 additions & 5 deletions src/coreclr/jit/lsraarm64.cpp
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Original file line numberDiff line numberDiff line change
Expand Up@@ -180,7 +180,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
unsigned int registersNeeded,
regMaskTP* allConsecutiveCandidates)
{
if (BitOperations::PopCount(candidates) < registersNeeded)
if (PopCount(candidates) < registersNeeded)
{
// There is no way the register demanded can be satisfied for this RefPosition
// based on the candidates from which it can allocate a register.
Expand All@@ -205,7 +205,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
do
{
// From LSB, find the first available register (bit `1`)
regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(currAvailableRegs));
regAvailableStartIndex = BitScanForward(currAvailableRegs);
regMaskTP startMask = (1ULL << regAvailableStartIndex) - 1;

// Mask all the bits that are processed from LSB thru regAvailableStart until the last `1`.
Expand All@@ -223,7 +223,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
}
else
{
regAvailableEndIndex = BitOperations::BitScanForward(static_cast<DWORD64>(maskProcessed));
regAvailableEndIndex = BitScanForward(maskProcessed);
}
regMaskTP endMask = (1ULL << regAvailableEndIndex) - 1;

Expand DownExpand Up@@ -335,7 +335,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
do
{
// From LSB, find the first available register (bit `1`)
regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(unprocessedRegs));
regAvailableStartIndex = BitScanForward(unprocessedRegs);

// For the current range, find how many registers are free vs. busy
regMaskTP maskForCurRange = RBM_NONE;
Expand DownExpand Up@@ -370,7 +370,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
// In the given range, there are some free registers available. Calculate how many registers
// will need spilling if this range is picked.

int curSpillRegs = registersNeeded - BitOperations::PopCount(maskForCurRange);
int curSpillRegs = registersNeeded - PopCount(maskForCurRange);
if (curSpillRegs < maxSpillRegs)
{
consecutiveResultForBusy = 1ULL << regAvailableStartIndex;
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/jit/lsrabuild.cpp
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Expand Up@@ -2898,7 +2898,7 @@ void LinearScan::stressSetRandomParameterPreferences()

// Select a random register from all possible parameter registers
// (of the right type). Preference this parameter to that register.
unsigned numBits = BitOperations::PopCount(*regs);
unsigned numBits = PopCount(*regs);
if (numBits == 0)
{
continue;
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/jit/regset.cpp
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Expand Up@@ -960,7 +960,7 @@ regMaskSmall genRegMaskFromCalleeSavedMask(unsigned short calleeSaveMask)
regMaskSmall res = 0;
for (int i = 0; i < CNT_CALLEE_SAVED; i++)
{
if ((calleeSaveMask & ((regMaskTP)1 << i)) != 0)
if ((calleeSaveMask & (1 << i)) != 0)
{
res |= raRbmCalleeSaveOrder[i];
}
Expand Down
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}
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(function(){
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var __m = "github.com";
var __re = new RegExp('^' + "github\\.com" + '

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Handle more than 64 registers - Part 1#101950

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 Merged

kunalspathak
merged 10 commits into

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May 11, 2024
 Merged


Handle more than 64 registers - Part 1
#101950
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f436712

Convert regMaskTP for ARM64 to struct with single field


kunalspathak May 6, 2024
8ff7508

Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()


kunalspathak May 6, 2024
7ac4137

minor fix


kunalspathak May 6, 2024
0144cb0

review feedback


kunalspathak May 8, 2024
81b26c6

fix the TP regression from 1.5% -> 0.5%


kunalspathak May 8, 2024
261ab5d

Pass by value


kunalspathak May 8, 2024
639290c

jit format


kunalspathak May 9, 2024
28b457d

review feedback


kunalspathak May 10, 2024
0a0e61d

Remove FORCEINLINE


kunalspathak May 10, 2024
8fdbf3f

Remove setLow()


kunalspathak May 10, 2024

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9 changes: 4 additions & 5 deletions
src/coreclr/jit/codegencommon.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -3829,9 +3829,9 @@ void CodeGen::genZeroInitFltRegs(const regMaskTP& initFltRegs, const regMaskTP&

 // Iterate through float/double registers and initialize them to 0 or
 // copy from already initialized register of the same type.
 regMaskTP regMask = genRegMask(REG_FP_FIRST);
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initFltRegs)
 {
 // Do we have a float register already set to 0?
Expand DownExpand Up@@ -5732,10 +5732,9 @@ void CodeGen::genFnProlog()

 if (initRegs)
 {
 regMaskTP regMask = 0x1;

 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initRegs)
 {
 // Check if we have already zeroed this register
Expand Down

64 changes: 61 additions & 3 deletions
src/coreclr/jit/compiler.hpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -99,6 +99,33 @@ inline bool genExactlyOneBit(T value)
 return ((value != 0) && genMaxOneBit(value));
}

#ifdef TARGET_ARM64
inline regMaskTP genFindLowestBit(regMaskTP value)
{
 return regMaskTP(genFindLowestBit(value.getLow()));
}

/*****************************************************************************
 *
 * Return true if the given value has exactly zero or one bits set.
 */

inline bool genMaxOneBit(regMaskTP value)
{
 return genMaxOneBit(value.getLow());
}

/*****************************************************************************
 *
 * Return true if the given value has exactly one bit set.
 */

inline bool genExactlyOneBit(regMaskTP value)
{
 return genExactlyOneBit(value.getLow());
}
#endif

/*****************************************************************************
 *
 * Given a value that has exactly one bit set, return the position of that
Expand DownExpand Up@@ -147,6 +174,13 @@ inline unsigned genCountBits(uint64_t bits)
 return BitOperations::PopCount(bits);
}

#ifdef TARGET_ARM64
inline unsigned genCountBits(regMaskTP mask)
{
 return BitOperations::PopCount(mask.getLow());
}
#endif

/*****************************************************************************
 *
 * A rather simple routine that counts the number of bits in a given number.
Expand DownExpand Up@@ -914,11 +948,18 @@ inline regNumber genRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)genLog2(mask);
#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)genLog2(mask.getLow());

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask.getLow());

#else
 regNumber regNum = (regNumber)genLog2(mask);

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask);
#endif

 return regNum;
}
Expand All@@ -940,7 +981,8 @@ inline regNumber genFirstRegNumFromMaskAndToggle(regMaskTP& mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 mask ^= genRegMask(regNum);

 return regNum;
Expand All@@ -962,7 +1004,7 @@ inline regNumber genFirstRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 return regNum;
}
Expand DownExpand Up@@ -4463,30 +4505,46 @@ inline void* operator new[](size_t sz, Compiler* compiler, CompMemKind cmk)

inline void printRegMask(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_ALL_FMT, mask.getLow());
#else
 printf(REG_MASK_ALL_FMT, mask);
#endif
}

inline char* regMaskToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask.getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask);
#endif

 return regmask;
}

inline void printRegMaskInt(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif
}

inline char* regMaskIntToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif

 return regmask;
}
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/emit.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -3470,7 +3470,7 @@ void emitter::emitDispRegSet(regMaskTP regs)
 continue;
 }

 regs -= curReg;
 regs ^= curReg;

 if (sp)
 {
Expand DownExpand Up@@ -3828,8 +3828,8 @@ void emitter::emitDispGCRegDelta(const char* title, regMaskTP prevRegs, regMaskT
 {
 emitDispGCDeltaTitle(title);
 regMaskTP sameRegs = prevRegs & curRegs;
 regMaskTP removedRegs = prevRegs - sameRegs;
 regMaskTP addedRegs = curRegs - sameRegs;
 regMaskTP removedRegs = prevRegs ^ sameRegs;
 regMaskTP addedRegs = curRegs ^ sameRegs;
 if (removedRegs != RBM_NONE)
 {
 printf(" -");
Expand DownExpand Up@@ -8920,7 +8920,7 @@ void emitter::emitUpdateLiveGCregs(GCtype gcType, regMaskTP regs, BYTE* addr)
 emitGCregDeadUpd(reg, addr);
 }

 chg -= bit;
 chg ^= bit;
 } while (chg);

 assert(emitThisXXrefRegs == regs);
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/gcencode.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -4667,7 +4667,7 @@ void GCInfo::gcInfoRecordGCRegStateChange(GcInfoEncoder* gcInfoEncoder,
 }

 // Turn the bit we've just generated off and continue.
 regMask -= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 regMask ^= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 }
}

Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsra.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -13609,7 +13609,7 @@ regMaskTP LinearScan::RegisterSelection::select(Interval* current
 &overallLimitCandidates);
 assert(limitConsecutiveResult != RBM_NONE);

 unsigned startRegister = BitOperations::BitScanForward(limitConsecutiveResult);
 unsigned startRegister = BitScanForward(limitConsecutiveResult);

 regMaskTP registersNeededMask = (1ULL << refPosition->regCount) - 1;
 candidates |= (registersNeededMask << startRegister);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/lsra.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -794,8 +794,8 @@ class LinearScan : public LinearScanInterface
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R3 | RBM_R4 | RBM_R5);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_F0 | RBM_F1 | RBM_F2 | RBM_F16 | RBM_F17);
#elif defined(TARGET_ARM64)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
 static constexpr regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static constexpr regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
#elif defined(TARGET_X86)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_EAX | RBM_ECX | RBM_EDI);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM6 | RBM_XMM7);
Expand Down

10 changes: 5 additions & 5 deletions
src/coreclr/jit/lsraarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -180,7 +180,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 unsigned int registersNeeded,
 regMaskTP* allConsecutiveCandidates)
{
 if (BitOperations::PopCount(candidates) < registersNeeded)
 if (PopCount(candidates) < registersNeeded)
 {
 // There is no way the register demanded can be satisfied for this RefPosition
 // based on the candidates from which it can allocate a register.
Expand All@@ -205,7 +205,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(currAvailableRegs));
 regAvailableStartIndex = BitScanForward(currAvailableRegs);
 regMaskTP startMask = (1ULL << regAvailableStartIndex) - 1;

 // Mask all the bits that are processed from LSB thru regAvailableStart until the last `1`.
Expand All@@ -223,7 +223,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 }
 else
 {
 regAvailableEndIndex = BitOperations::BitScanForward(static_cast<DWORD64>(maskProcessed));
 regAvailableEndIndex = BitScanForward(maskProcessed);
 }
 regMaskTP endMask = (1ULL << regAvailableEndIndex) - 1;

Expand DownExpand Up@@ -335,7 +335,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(unprocessedRegs));
 regAvailableStartIndex = BitScanForward(unprocessedRegs);

 // For the current range, find how many registers are free vs. busy
 regMaskTP maskForCurRange = RBM_NONE;
Expand DownExpand Up@@ -370,7 +370,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 // In the given range, there are some free registers available. Calculate how many registers
 // will need spilling if this range is picked.

 int curSpillRegs = registersNeeded - BitOperations::PopCount(maskForCurRange);
 int curSpillRegs = registersNeeded - PopCount(maskForCurRange);
 if (curSpillRegs < maxSpillRegs)
 {
 consecutiveResultForBusy = 1ULL << regAvailableStartIndex;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsrabuild.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -2898,7 +2898,7 @@ void LinearScan::stressSetRandomParameterPreferences()

 // Select a random register from all possible parameter registers
 // (of the right type). Preference this parameter to that register.
 unsigned numBits = BitOperations::PopCount(*regs);
 unsigned numBits = PopCount(*regs);
 if (numBits == 0)
 {
 continue;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/regset.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -960,7 +960,7 @@ regMaskSmall genRegMaskFromCalleeSavedMask(unsigned short calleeSaveMask)
 regMaskSmall res = 0;
 for (int i = 0; i < CNT_CALLEE_SAVED; i++)
 {
 if ((calleeSaveMask & ((regMaskTP)1 << i)) != 0)
 if ((calleeSaveMask & (1 << i)) != 0)
 {
 res |= raRbmCalleeSaveOrder[i];
 }
Expand Down
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Handle more than 64 registers - Part 1
#101950
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f436712

Convert regMaskTP for ARM64 to struct with single field


kunalspathak May 6, 2024
8ff7508

Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()


kunalspathak May 6, 2024
7ac4137

minor fix


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review feedback


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fix the TP regression from 1.5% -> 0.5%


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Pass by value


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639290c

jit format


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Remove FORCEINLINE


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Remove setLow()


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9 changes: 4 additions & 5 deletions
src/coreclr/jit/codegencommon.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -3829,9 +3829,9 @@ void CodeGen::genZeroInitFltRegs(const regMaskTP& initFltRegs, const regMaskTP&

 // Iterate through float/double registers and initialize them to 0 or
 // copy from already initialized register of the same type.
 regMaskTP regMask = genRegMask(REG_FP_FIRST);
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initFltRegs)
 {
 // Do we have a float register already set to 0?
Expand DownExpand Up@@ -5732,10 +5732,9 @@ void CodeGen::genFnProlog()

 if (initRegs)
 {
 regMaskTP regMask = 0x1;

 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initRegs)
 {
 // Check if we have already zeroed this register
Expand Down

64 changes: 61 additions & 3 deletions
src/coreclr/jit/compiler.hpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -99,6 +99,33 @@ inline bool genExactlyOneBit(T value)
 return ((value != 0) && genMaxOneBit(value));
}

#ifdef TARGET_ARM64
inline regMaskTP genFindLowestBit(regMaskTP value)
{
 return regMaskTP(genFindLowestBit(value.getLow()));
}

/*****************************************************************************
 *
 * Return true if the given value has exactly zero or one bits set.
 */

inline bool genMaxOneBit(regMaskTP value)
{
 return genMaxOneBit(value.getLow());
}

/*****************************************************************************
 *
 * Return true if the given value has exactly one bit set.
 */

inline bool genExactlyOneBit(regMaskTP value)
{
 return genExactlyOneBit(value.getLow());
}
#endif

/*****************************************************************************
 *
 * Given a value that has exactly one bit set, return the position of that
Expand DownExpand Up@@ -147,6 +174,13 @@ inline unsigned genCountBits(uint64_t bits)
 return BitOperations::PopCount(bits);
}

#ifdef TARGET_ARM64
inline unsigned genCountBits(regMaskTP mask)
{
 return BitOperations::PopCount(mask.getLow());
}
#endif

/*****************************************************************************
 *
 * A rather simple routine that counts the number of bits in a given number.
Expand DownExpand Up@@ -914,11 +948,18 @@ inline regNumber genRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)genLog2(mask);
#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)genLog2(mask.getLow());

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask.getLow());

#else
 regNumber regNum = (regNumber)genLog2(mask);

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask);
#endif

 return regNum;
}
Expand All@@ -940,7 +981,8 @@ inline regNumber genFirstRegNumFromMaskAndToggle(regMaskTP& mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 mask ^= genRegMask(regNum);

 return regNum;
Expand All@@ -962,7 +1004,7 @@ inline regNumber genFirstRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 return regNum;
}
Expand DownExpand Up@@ -4463,30 +4505,46 @@ inline void* operator new[](size_t sz, Compiler* compiler, CompMemKind cmk)

inline void printRegMask(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_ALL_FMT, mask.getLow());
#else
 printf(REG_MASK_ALL_FMT, mask);
#endif
}

inline char* regMaskToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask.getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask);
#endif

 return regmask;
}

inline void printRegMaskInt(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif
}

inline char* regMaskIntToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif

 return regmask;
}
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/emit.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -3470,7 +3470,7 @@ void emitter::emitDispRegSet(regMaskTP regs)
 continue;
 }

 regs -= curReg;
 regs ^= curReg;

 if (sp)
 {
Expand DownExpand Up@@ -3828,8 +3828,8 @@ void emitter::emitDispGCRegDelta(const char* title, regMaskTP prevRegs, regMaskT
 {
 emitDispGCDeltaTitle(title);
 regMaskTP sameRegs = prevRegs & curRegs;
 regMaskTP removedRegs = prevRegs - sameRegs;
 regMaskTP addedRegs = curRegs - sameRegs;
 regMaskTP removedRegs = prevRegs ^ sameRegs;
 regMaskTP addedRegs = curRegs ^ sameRegs;
 if (removedRegs != RBM_NONE)
 {
 printf(" -");
Expand DownExpand Up@@ -8920,7 +8920,7 @@ void emitter::emitUpdateLiveGCregs(GCtype gcType, regMaskTP regs, BYTE* addr)
 emitGCregDeadUpd(reg, addr);
 }

 chg -= bit;
 chg ^= bit;
 } while (chg);

 assert(emitThisXXrefRegs == regs);
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/gcencode.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -4667,7 +4667,7 @@ void GCInfo::gcInfoRecordGCRegStateChange(GcInfoEncoder* gcInfoEncoder,
 }

 // Turn the bit we've just generated off and continue.
 regMask -= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 regMask ^= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 }
}

Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsra.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -13609,7 +13609,7 @@ regMaskTP LinearScan::RegisterSelection::select(Interval* current
 &overallLimitCandidates);
 assert(limitConsecutiveResult != RBM_NONE);

 unsigned startRegister = BitOperations::BitScanForward(limitConsecutiveResult);
 unsigned startRegister = BitScanForward(limitConsecutiveResult);

 regMaskTP registersNeededMask = (1ULL << refPosition->regCount) - 1;
 candidates |= (registersNeededMask << startRegister);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/lsra.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -794,8 +794,8 @@ class LinearScan : public LinearScanInterface
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R3 | RBM_R4 | RBM_R5);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_F0 | RBM_F1 | RBM_F2 | RBM_F16 | RBM_F17);
#elif defined(TARGET_ARM64)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
 static constexpr regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static constexpr regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
#elif defined(TARGET_X86)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_EAX | RBM_ECX | RBM_EDI);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM6 | RBM_XMM7);
Expand Down

10 changes: 5 additions & 5 deletions
src/coreclr/jit/lsraarm64.cpp

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -180,7 +180,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 unsigned int registersNeeded,
 regMaskTP* allConsecutiveCandidates)
{
 if (BitOperations::PopCount(candidates) < registersNeeded)
 if (PopCount(candidates) < registersNeeded)
 {
 // There is no way the register demanded can be satisfied for this RefPosition
 // based on the candidates from which it can allocate a register.
Expand All@@ -205,7 +205,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(currAvailableRegs));
 regAvailableStartIndex = BitScanForward(currAvailableRegs);
 regMaskTP startMask = (1ULL << regAvailableStartIndex) - 1;

 // Mask all the bits that are processed from LSB thru regAvailableStart until the last `1`.
Expand All@@ -223,7 +223,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 }
 else
 {
 regAvailableEndIndex = BitOperations::BitScanForward(static_cast<DWORD64>(maskProcessed));
 regAvailableEndIndex = BitScanForward(maskProcessed);
 }
 regMaskTP endMask = (1ULL << regAvailableEndIndex) - 1;

Expand DownExpand Up@@ -335,7 +335,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(unprocessedRegs));
 regAvailableStartIndex = BitScanForward(unprocessedRegs);

 // For the current range, find how many registers are free vs. busy
 regMaskTP maskForCurRange = RBM_NONE;
Expand DownExpand Up@@ -370,7 +370,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 // In the given range, there are some free registers available. Calculate how many registers
 // will need spilling if this range is picked.

 int curSpillRegs = registersNeeded - BitOperations::PopCount(maskForCurRange);
 int curSpillRegs = registersNeeded - PopCount(maskForCurRange);
 if (curSpillRegs < maxSpillRegs)
 {
 consecutiveResultForBusy = 1ULL << regAvailableStartIndex;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsrabuild.cpp

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -2898,7 +2898,7 @@ void LinearScan::stressSetRandomParameterPreferences()

 // Select a random register from all possible parameter registers
 // (of the right type). Preference this parameter to that register.
 unsigned numBits = BitOperations::PopCount(*regs);
 unsigned numBits = PopCount(*regs);
 if (numBits == 0)
 {
 continue;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/regset.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -960,7 +960,7 @@ regMaskSmall genRegMaskFromCalleeSavedMask(unsigned short calleeSaveMask)
 regMaskSmall res = 0;
 for (int i = 0; i < CNT_CALLEE_SAVED; i++)
 {
 if ((calleeSaveMask & ((regMaskTP)1 << i)) != 0)
 if ((calleeSaveMask & (1 << i)) != 0)
 {
 res |= raRbmCalleeSaveOrder[i];
 }
Expand Down
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if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Highlight search terms from Google/DuckDuckGo/Bing referrer\n(function() {\n var ref = document.referrer;\n var terms = [];\n \n if (ref.includes('google.com') || ref.includes('duckduckgo.com') || ref.includes('bing.com')) {\n var url = new URL(ref);\n var q = url.searchParams.get('q') || url.searchParams.get('p');\n if (q) {\n terms = q.split(/\\s+/).filter(function(t) { return t.length > 2; });\n }\n }\n \n if (terms.length === 0) return;\n \n var style = document.createElement('style');\n style.textContent = '.userscript-highlight { background: #fbbf24; color: #1a1a2e; padding: 1px 3px; border-radius: 2px; }';\n document.head.appendChild(style);\n \n function highlight(node) {\n if (node.nodeType === 3) { // text node\n var text = node.textContent;\n var found = false;\n terms.forEach(function(term) {\n var regex = new RegExp('(' + term.replace(/[.*+?^${}()|[\\]\\\\]/g, '\\\\') + ')', 'gi');\n if (regex.test(text)) {\n found = true;\n var frag = document.createDocumentFragment();\n var parts = text.split(regex);\n parts.forEach(function(part, i) {\n if (i % 2 === 0) {\n frag.appendChild(document.createTextNode(part));\n } else {\n var span = document.createElement('span');\n span.className = 'userscript-highlight';\n span.textContent = part;\n frag.appendChild(span);\n }\n });\n node.parentNode.replaceChild(frag, node);\n }\n });\n } else if (node.nodeType === 1 && node.childNodes) { // element\n var skipTags = ['SCRIPT', 'STYLE', 'NOSCRIPT', 'TEXTAREA', 'INPUT', 'SELECT'];\n if (!skipTags.includes(node.tagName)) {\n Array.from(node.childNodes).forEach(highlight);\n }\n }\n }\n \n highlight(document.body);\n \n // Re-highlight on dynamic content\n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1 || node.nodeType === 3) highlight(node);\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Highlight Search Terms");
}
} catch(__e) { console.warn('[Userscript:Highlight Search Terms]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

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Handle more than 64 registers - Part 1#101950

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 Merged

kunalspathak
merged 10 commits into

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May 11, 2024
 Merged


Handle more than 64 registers - Part 1
#101950
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f436712

Convert regMaskTP for ARM64 to struct with single field


kunalspathak May 6, 2024
8ff7508

Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()


kunalspathak May 6, 2024
7ac4137

minor fix


kunalspathak May 6, 2024
0144cb0

review feedback


kunalspathak May 8, 2024
81b26c6

fix the TP regression from 1.5% -> 0.5%


kunalspathak May 8, 2024
261ab5d

Pass by value


kunalspathak May 8, 2024
639290c

jit format


kunalspathak May 9, 2024
28b457d

review feedback


kunalspathak May 10, 2024
0a0e61d

Remove FORCEINLINE


kunalspathak May 10, 2024
8fdbf3f

Remove setLow()


kunalspathak May 10, 2024

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9 changes: 4 additions & 5 deletions
src/coreclr/jit/codegencommon.cpp

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -3829,9 +3829,9 @@ void CodeGen::genZeroInitFltRegs(const regMaskTP& initFltRegs, const regMaskTP&

 // Iterate through float/double registers and initialize them to 0 or
 // copy from already initialized register of the same type.
 regMaskTP regMask = genRegMask(REG_FP_FIRST);
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initFltRegs)
 {
 // Do we have a float register already set to 0?
Expand DownExpand Up@@ -5732,10 +5732,9 @@ void CodeGen::genFnProlog()

 if (initRegs)
 {
 regMaskTP regMask = 0x1;

 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initRegs)
 {
 // Check if we have already zeroed this register
Expand Down

64 changes: 61 additions & 3 deletions
src/coreclr/jit/compiler.hpp

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -99,6 +99,33 @@ inline bool genExactlyOneBit(T value)
 return ((value != 0) && genMaxOneBit(value));
}

#ifdef TARGET_ARM64
inline regMaskTP genFindLowestBit(regMaskTP value)
{
 return regMaskTP(genFindLowestBit(value.getLow()));
}

/*****************************************************************************
 *
 * Return true if the given value has exactly zero or one bits set.
 */

inline bool genMaxOneBit(regMaskTP value)
{
 return genMaxOneBit(value.getLow());
}

/*****************************************************************************
 *
 * Return true if the given value has exactly one bit set.
 */

inline bool genExactlyOneBit(regMaskTP value)
{
 return genExactlyOneBit(value.getLow());
}
#endif

/*****************************************************************************
 *
 * Given a value that has exactly one bit set, return the position of that
Expand DownExpand Up@@ -147,6 +174,13 @@ inline unsigned genCountBits(uint64_t bits)
 return BitOperations::PopCount(bits);
}

#ifdef TARGET_ARM64
inline unsigned genCountBits(regMaskTP mask)
{
 return BitOperations::PopCount(mask.getLow());
}
#endif

/*****************************************************************************
 *
 * A rather simple routine that counts the number of bits in a given number.
Expand DownExpand Up@@ -914,11 +948,18 @@ inline regNumber genRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)genLog2(mask);
#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)genLog2(mask.getLow());

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask.getLow());

#else
 regNumber regNum = (regNumber)genLog2(mask);

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask);
#endif

 return regNum;
}
Expand All@@ -940,7 +981,8 @@ inline regNumber genFirstRegNumFromMaskAndToggle(regMaskTP& mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 mask ^= genRegMask(regNum);

 return regNum;
Expand All@@ -962,7 +1004,7 @@ inline regNumber genFirstRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 return regNum;
}
Expand DownExpand Up@@ -4463,30 +4505,46 @@ inline void* operator new[](size_t sz, Compiler* compiler, CompMemKind cmk)

inline void printRegMask(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_ALL_FMT, mask.getLow());
#else
 printf(REG_MASK_ALL_FMT, mask);
#endif
}

inline char* regMaskToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask.getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask);
#endif

 return regmask;
}

inline void printRegMaskInt(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif
}

inline char* regMaskIntToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif

 return regmask;
}
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/emit.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -3470,7 +3470,7 @@ void emitter::emitDispRegSet(regMaskTP regs)
 continue;
 }

 regs -= curReg;
 regs ^= curReg;

 if (sp)
 {
Expand DownExpand Up@@ -3828,8 +3828,8 @@ void emitter::emitDispGCRegDelta(const char* title, regMaskTP prevRegs, regMaskT
 {
 emitDispGCDeltaTitle(title);
 regMaskTP sameRegs = prevRegs & curRegs;
 regMaskTP removedRegs = prevRegs - sameRegs;
 regMaskTP addedRegs = curRegs - sameRegs;
 regMaskTP removedRegs = prevRegs ^ sameRegs;
 regMaskTP addedRegs = curRegs ^ sameRegs;
 if (removedRegs != RBM_NONE)
 {
 printf(" -");
Expand DownExpand Up@@ -8920,7 +8920,7 @@ void emitter::emitUpdateLiveGCregs(GCtype gcType, regMaskTP regs, BYTE* addr)
 emitGCregDeadUpd(reg, addr);
 }

 chg -= bit;
 chg ^= bit;
 } while (chg);

 assert(emitThisXXrefRegs == regs);
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/gcencode.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -4667,7 +4667,7 @@ void GCInfo::gcInfoRecordGCRegStateChange(GcInfoEncoder* gcInfoEncoder,
 }

 // Turn the bit we've just generated off and continue.
 regMask -= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 regMask ^= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 }
}

Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsra.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -13609,7 +13609,7 @@ regMaskTP LinearScan::RegisterSelection::select(Interval* current
 &overallLimitCandidates);
 assert(limitConsecutiveResult != RBM_NONE);

 unsigned startRegister = BitOperations::BitScanForward(limitConsecutiveResult);
 unsigned startRegister = BitScanForward(limitConsecutiveResult);

 regMaskTP registersNeededMask = (1ULL << refPosition->regCount) - 1;
 candidates |= (registersNeededMask << startRegister);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/lsra.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -794,8 +794,8 @@ class LinearScan : public LinearScanInterface
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R3 | RBM_R4 | RBM_R5);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_F0 | RBM_F1 | RBM_F2 | RBM_F16 | RBM_F17);
#elif defined(TARGET_ARM64)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
 static constexpr regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static constexpr regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
#elif defined(TARGET_X86)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_EAX | RBM_ECX | RBM_EDI);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM6 | RBM_XMM7);
Expand Down

10 changes: 5 additions & 5 deletions
src/coreclr/jit/lsraarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -180,7 +180,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 unsigned int registersNeeded,
 regMaskTP* allConsecutiveCandidates)
{
 if (BitOperations::PopCount(candidates) < registersNeeded)
 if (PopCount(candidates) < registersNeeded)
 {
 // There is no way the register demanded can be satisfied for this RefPosition
 // based on the candidates from which it can allocate a register.
Expand All@@ -205,7 +205,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(currAvailableRegs));
 regAvailableStartIndex = BitScanForward(currAvailableRegs);
 regMaskTP startMask = (1ULL << regAvailableStartIndex) - 1;

 // Mask all the bits that are processed from LSB thru regAvailableStart until the last `1`.
Expand All@@ -223,7 +223,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 }
 else
 {
 regAvailableEndIndex = BitOperations::BitScanForward(static_cast<DWORD64>(maskProcessed));
 regAvailableEndIndex = BitScanForward(maskProcessed);
 }
 regMaskTP endMask = (1ULL << regAvailableEndIndex) - 1;

Expand DownExpand Up@@ -335,7 +335,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(unprocessedRegs));
 regAvailableStartIndex = BitScanForward(unprocessedRegs);

 // For the current range, find how many registers are free vs. busy
 regMaskTP maskForCurRange = RBM_NONE;
Expand DownExpand Up@@ -370,7 +370,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 // In the given range, there are some free registers available. Calculate how many registers
 // will need spilling if this range is picked.

 int curSpillRegs = registersNeeded - BitOperations::PopCount(maskForCurRange);
 int curSpillRegs = registersNeeded - PopCount(maskForCurRange);
 if (curSpillRegs < maxSpillRegs)
 {
 consecutiveResultForBusy = 1ULL << regAvailableStartIndex;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsrabuild.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -2898,7 +2898,7 @@ void LinearScan::stressSetRandomParameterPreferences()

 // Select a random register from all possible parameter registers
 // (of the right type). Preference this parameter to that register.
 unsigned numBits = BitOperations::PopCount(*regs);
 unsigned numBits = PopCount(*regs);
 if (numBits == 0)
 {
 continue;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/regset.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -960,7 +960,7 @@ regMaskSmall genRegMaskFromCalleeSavedMask(unsigned short calleeSaveMask)
 regMaskSmall res = 0;
 for (int i = 0; i < CNT_CALLEE_SAVED; i++)
 {
 if ((calleeSaveMask & ((regMaskTP)1 << i)) != 0)
 if ((calleeSaveMask & (1 << i)) != 0)
 {
 res |= raRbmCalleeSaveOrder[i];
 }
Expand Down
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, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Strip utm_, fbclid, gclid, etc. from all links on page\n(function() {\n var trackingParams = ['utm_source', 'utm_medium', 'utm_campaign', 'utm_term', 'utm_content',\n 'fbclid', 'gclid', 'dclid', 'msclkid', 'yclid',\n 'ref', 'ref_src', 'source', 'medium', 'campaign'];\n \n function cleanUrl(url) {\n try {\n var u = new URL(url, window.location.origin);\n var changed = false;\n trackingParams.forEach(function(p) {\n if (u.searchParams.has(p)) {\n u.searchParams.delete(p);\n changed = true;\n }\n });\n return changed ? u.toString() : url;\n } catch (e) {\n return url;\n }\n }\n \n function cleanLinks() {\n document.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n \n cleanLinks();\n \n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1) {\n if (node.tagName === 'A') cleanLinks();\n node.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Remove Tracking Parameters from Links");
}
} catch(__e) { console.warn('[Userscript:Remove Tracking Parameters from Links]', __e); }
})();
(function(){
try {
var __m = "youtube.com";
var __re = new RegExp('^' + "youtube\\.com" + '

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 Merged

kunalspathak
merged 10 commits into

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May 11, 2024
 Merged


Handle more than 64 registers - Part 1
#101950
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f436712

Convert regMaskTP for ARM64 to struct with single field


kunalspathak May 6, 2024
8ff7508

Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()


kunalspathak May 6, 2024
7ac4137

minor fix


kunalspathak May 6, 2024
0144cb0

review feedback


kunalspathak May 8, 2024
81b26c6

fix the TP regression from 1.5% -> 0.5%


kunalspathak May 8, 2024
261ab5d

Pass by value


kunalspathak May 8, 2024
639290c

jit format


kunalspathak May 9, 2024
28b457d

review feedback


kunalspathak May 10, 2024
0a0e61d

Remove FORCEINLINE


kunalspathak May 10, 2024
8fdbf3f

Remove setLow()


kunalspathak May 10, 2024

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9 changes: 4 additions & 5 deletions
src/coreclr/jit/codegencommon.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -3829,9 +3829,9 @@ void CodeGen::genZeroInitFltRegs(const regMaskTP& initFltRegs, const regMaskTP&

 // Iterate through float/double registers and initialize them to 0 or
 // copy from already initialized register of the same type.
 regMaskTP regMask = genRegMask(REG_FP_FIRST);
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initFltRegs)
 {
 // Do we have a float register already set to 0?
Expand DownExpand Up@@ -5732,10 +5732,9 @@ void CodeGen::genFnProlog()

 if (initRegs)
 {
 regMaskTP regMask = 0x1;

 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initRegs)
 {
 // Check if we have already zeroed this register
Expand Down

64 changes: 61 additions & 3 deletions
src/coreclr/jit/compiler.hpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -99,6 +99,33 @@ inline bool genExactlyOneBit(T value)
 return ((value != 0) && genMaxOneBit(value));
}

#ifdef TARGET_ARM64
inline regMaskTP genFindLowestBit(regMaskTP value)
{
 return regMaskTP(genFindLowestBit(value.getLow()));
}

/*****************************************************************************
 *
 * Return true if the given value has exactly zero or one bits set.
 */

inline bool genMaxOneBit(regMaskTP value)
{
 return genMaxOneBit(value.getLow());
}

/*****************************************************************************
 *
 * Return true if the given value has exactly one bit set.
 */

inline bool genExactlyOneBit(regMaskTP value)
{
 return genExactlyOneBit(value.getLow());
}
#endif

/*****************************************************************************
 *
 * Given a value that has exactly one bit set, return the position of that
Expand DownExpand Up@@ -147,6 +174,13 @@ inline unsigned genCountBits(uint64_t bits)
 return BitOperations::PopCount(bits);
}

#ifdef TARGET_ARM64
inline unsigned genCountBits(regMaskTP mask)
{
 return BitOperations::PopCount(mask.getLow());
}
#endif

/*****************************************************************************
 *
 * A rather simple routine that counts the number of bits in a given number.
Expand DownExpand Up@@ -914,11 +948,18 @@ inline regNumber genRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)genLog2(mask);
#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)genLog2(mask.getLow());

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask.getLow());

#else
 regNumber regNum = (regNumber)genLog2(mask);

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask);
#endif

 return regNum;
}
Expand All@@ -940,7 +981,8 @@ inline regNumber genFirstRegNumFromMaskAndToggle(regMaskTP& mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 mask ^= genRegMask(regNum);

 return regNum;
Expand All@@ -962,7 +1004,7 @@ inline regNumber genFirstRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 return regNum;
}
Expand DownExpand Up@@ -4463,30 +4505,46 @@ inline void* operator new[](size_t sz, Compiler* compiler, CompMemKind cmk)

inline void printRegMask(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_ALL_FMT, mask.getLow());
#else
 printf(REG_MASK_ALL_FMT, mask);
#endif
}

inline char* regMaskToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask.getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask);
#endif

 return regmask;
}

inline void printRegMaskInt(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif
}

inline char* regMaskIntToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif

 return regmask;
}
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/emit.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -3470,7 +3470,7 @@ void emitter::emitDispRegSet(regMaskTP regs)
 continue;
 }

 regs -= curReg;
 regs ^= curReg;

 if (sp)
 {
Expand DownExpand Up@@ -3828,8 +3828,8 @@ void emitter::emitDispGCRegDelta(const char* title, regMaskTP prevRegs, regMaskT
 {
 emitDispGCDeltaTitle(title);
 regMaskTP sameRegs = prevRegs & curRegs;
 regMaskTP removedRegs = prevRegs - sameRegs;
 regMaskTP addedRegs = curRegs - sameRegs;
 regMaskTP removedRegs = prevRegs ^ sameRegs;
 regMaskTP addedRegs = curRegs ^ sameRegs;
 if (removedRegs != RBM_NONE)
 {
 printf(" -");
Expand DownExpand Up@@ -8920,7 +8920,7 @@ void emitter::emitUpdateLiveGCregs(GCtype gcType, regMaskTP regs, BYTE* addr)
 emitGCregDeadUpd(reg, addr);
 }

 chg -= bit;
 chg ^= bit;
 } while (chg);

 assert(emitThisXXrefRegs == regs);
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/gcencode.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -4667,7 +4667,7 @@ void GCInfo::gcInfoRecordGCRegStateChange(GcInfoEncoder* gcInfoEncoder,
 }

 // Turn the bit we've just generated off and continue.
 regMask -= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 regMask ^= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 }
}

Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsra.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -13609,7 +13609,7 @@ regMaskTP LinearScan::RegisterSelection::select(Interval* current
 &overallLimitCandidates);
 assert(limitConsecutiveResult != RBM_NONE);

 unsigned startRegister = BitOperations::BitScanForward(limitConsecutiveResult);
 unsigned startRegister = BitScanForward(limitConsecutiveResult);

 regMaskTP registersNeededMask = (1ULL << refPosition->regCount) - 1;
 candidates |= (registersNeededMask << startRegister);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/lsra.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -794,8 +794,8 @@ class LinearScan : public LinearScanInterface
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R3 | RBM_R4 | RBM_R5);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_F0 | RBM_F1 | RBM_F2 | RBM_F16 | RBM_F17);
#elif defined(TARGET_ARM64)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
 static constexpr regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static constexpr regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
#elif defined(TARGET_X86)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_EAX | RBM_ECX | RBM_EDI);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM6 | RBM_XMM7);
Expand Down

10 changes: 5 additions & 5 deletions
src/coreclr/jit/lsraarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -180,7 +180,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 unsigned int registersNeeded,
 regMaskTP* allConsecutiveCandidates)
{
 if (BitOperations::PopCount(candidates) < registersNeeded)
 if (PopCount(candidates) < registersNeeded)
 {
 // There is no way the register demanded can be satisfied for this RefPosition
 // based on the candidates from which it can allocate a register.
Expand All@@ -205,7 +205,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(currAvailableRegs));
 regAvailableStartIndex = BitScanForward(currAvailableRegs);
 regMaskTP startMask = (1ULL << regAvailableStartIndex) - 1;

 // Mask all the bits that are processed from LSB thru regAvailableStart until the last `1`.
Expand All@@ -223,7 +223,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 }
 else
 {
 regAvailableEndIndex = BitOperations::BitScanForward(static_cast<DWORD64>(maskProcessed));
 regAvailableEndIndex = BitScanForward(maskProcessed);
 }
 regMaskTP endMask = (1ULL << regAvailableEndIndex) - 1;

Expand DownExpand Up@@ -335,7 +335,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(unprocessedRegs));
 regAvailableStartIndex = BitScanForward(unprocessedRegs);

 // For the current range, find how many registers are free vs. busy
 regMaskTP maskForCurRange = RBM_NONE;
Expand DownExpand Up@@ -370,7 +370,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 // In the given range, there are some free registers available. Calculate how many registers
 // will need spilling if this range is picked.

 int curSpillRegs = registersNeeded - BitOperations::PopCount(maskForCurRange);
 int curSpillRegs = registersNeeded - PopCount(maskForCurRange);
 if (curSpillRegs < maxSpillRegs)
 {
 consecutiveResultForBusy = 1ULL << regAvailableStartIndex;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsrabuild.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -2898,7 +2898,7 @@ void LinearScan::stressSetRandomParameterPreferences()

 // Select a random register from all possible parameter registers
 // (of the right type). Preference this parameter to that register.
 unsigned numBits = BitOperations::PopCount(*regs);
 unsigned numBits = PopCount(*regs);
 if (numBits == 0)
 {
 continue;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/regset.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -960,7 +960,7 @@ regMaskSmall genRegMaskFromCalleeSavedMask(unsigned short calleeSaveMask)
 regMaskSmall res = 0;
 for (int i = 0; i < CNT_CALLEE_SAVED; i++)
 {
 if ((calleeSaveMask & ((regMaskTP)1 << i)) != 0)
 if ((calleeSaveMask & (1 << i)) != 0)
 {
 res |= raRbmCalleeSaveOrder[i];
 }
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Auto-enable theater mode on YouTube\n(function() {\n function tryTheater() {\n var btn = document.querySelector('button[aria-label=\"Theater mode\"], ytd-player #player button[title=\"Theater mode\"]');\n if (btn && !btn.classList.contains('activated')) {\n btn.click();\n }\n }\n \n // Try immediately\n tryTheater();\n \n // Try after navigation (SPA)\n var lastUrl = location.href;\n setInterval(function() {\n if (location.href !== lastUrl) {\n lastUrl = location.href;\n setTimeout(tryTheater, 500);\n }\n }, 1000);\n \n // Also try on player load\n var observer = new MutationObserver(tryTheater);\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "YouTube Theater Mode Default");
}
} catch(__e) { console.warn('[Userscript:YouTube Theater Mode Default]', __e); }
})();
(function(){
try {
var __m = "*";
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Handle more than 64 registers - Part 1#101950

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kunalspathak
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May 11, 2024
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Handle more than 64 registers - Part 1
#101950
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f436712

Convert regMaskTP for ARM64 to struct with single field


kunalspathak May 6, 2024
8ff7508

Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()


kunalspathak May 6, 2024
7ac4137

minor fix


kunalspathak May 6, 2024
0144cb0

review feedback


kunalspathak May 8, 2024
81b26c6

fix the TP regression from 1.5% -> 0.5%


kunalspathak May 8, 2024
261ab5d

Pass by value


kunalspathak May 8, 2024
639290c

jit format


kunalspathak May 9, 2024
28b457d

review feedback


kunalspathak May 10, 2024
0a0e61d

Remove FORCEINLINE


kunalspathak May 10, 2024
8fdbf3f

Remove setLow()


kunalspathak May 10, 2024

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9 changes: 4 additions & 5 deletions
src/coreclr/jit/codegencommon.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -3829,9 +3829,9 @@ void CodeGen::genZeroInitFltRegs(const regMaskTP& initFltRegs, const regMaskTP&

 // Iterate through float/double registers and initialize them to 0 or
 // copy from already initialized register of the same type.
 regMaskTP regMask = genRegMask(REG_FP_FIRST);
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initFltRegs)
 {
 // Do we have a float register already set to 0?
Expand DownExpand Up@@ -5732,10 +5732,9 @@ void CodeGen::genFnProlog()

 if (initRegs)
 {
 regMaskTP regMask = 0x1;

 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initRegs)
 {
 // Check if we have already zeroed this register
Expand Down

64 changes: 61 additions & 3 deletions
src/coreclr/jit/compiler.hpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -99,6 +99,33 @@ inline bool genExactlyOneBit(T value)
 return ((value != 0) && genMaxOneBit(value));
}

#ifdef TARGET_ARM64
inline regMaskTP genFindLowestBit(regMaskTP value)
{
 return regMaskTP(genFindLowestBit(value.getLow()));
}

/*****************************************************************************
 *
 * Return true if the given value has exactly zero or one bits set.
 */

inline bool genMaxOneBit(regMaskTP value)
{
 return genMaxOneBit(value.getLow());
}

/*****************************************************************************
 *
 * Return true if the given value has exactly one bit set.
 */

inline bool genExactlyOneBit(regMaskTP value)
{
 return genExactlyOneBit(value.getLow());
}
#endif

/*****************************************************************************
 *
 * Given a value that has exactly one bit set, return the position of that
Expand DownExpand Up@@ -147,6 +174,13 @@ inline unsigned genCountBits(uint64_t bits)
 return BitOperations::PopCount(bits);
}

#ifdef TARGET_ARM64
inline unsigned genCountBits(regMaskTP mask)
{
 return BitOperations::PopCount(mask.getLow());
}
#endif

/*****************************************************************************
 *
 * A rather simple routine that counts the number of bits in a given number.
Expand DownExpand Up@@ -914,11 +948,18 @@ inline regNumber genRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)genLog2(mask);
#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)genLog2(mask.getLow());

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask.getLow());

#else
 regNumber regNum = (regNumber)genLog2(mask);

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask);
#endif

 return regNum;
}
Expand All@@ -940,7 +981,8 @@ inline regNumber genFirstRegNumFromMaskAndToggle(regMaskTP& mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 mask ^= genRegMask(regNum);

 return regNum;
Expand All@@ -962,7 +1004,7 @@ inline regNumber genFirstRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 return regNum;
}
Expand DownExpand Up@@ -4463,30 +4505,46 @@ inline void* operator new[](size_t sz, Compiler* compiler, CompMemKind cmk)

inline void printRegMask(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_ALL_FMT, mask.getLow());
#else
 printf(REG_MASK_ALL_FMT, mask);
#endif
}

inline char* regMaskToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask.getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask);
#endif

 return regmask;
}

inline void printRegMaskInt(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif
}

inline char* regMaskIntToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif

 return regmask;
}
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/emit.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -3470,7 +3470,7 @@ void emitter::emitDispRegSet(regMaskTP regs)
 continue;
 }

 regs -= curReg;
 regs ^= curReg;

 if (sp)
 {
Expand DownExpand Up@@ -3828,8 +3828,8 @@ void emitter::emitDispGCRegDelta(const char* title, regMaskTP prevRegs, regMaskT
 {
 emitDispGCDeltaTitle(title);
 regMaskTP sameRegs = prevRegs & curRegs;
 regMaskTP removedRegs = prevRegs - sameRegs;
 regMaskTP addedRegs = curRegs - sameRegs;
 regMaskTP removedRegs = prevRegs ^ sameRegs;
 regMaskTP addedRegs = curRegs ^ sameRegs;
 if (removedRegs != RBM_NONE)
 {
 printf(" -");
Expand DownExpand Up@@ -8920,7 +8920,7 @@ void emitter::emitUpdateLiveGCregs(GCtype gcType, regMaskTP regs, BYTE* addr)
 emitGCregDeadUpd(reg, addr);
 }

 chg -= bit;
 chg ^= bit;
 } while (chg);

 assert(emitThisXXrefRegs == regs);
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/gcencode.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -4667,7 +4667,7 @@ void GCInfo::gcInfoRecordGCRegStateChange(GcInfoEncoder* gcInfoEncoder,
 }

 // Turn the bit we've just generated off and continue.
 regMask -= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 regMask ^= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 }
}

Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsra.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -13609,7 +13609,7 @@ regMaskTP LinearScan::RegisterSelection::select(Interval* current
 &overallLimitCandidates);
 assert(limitConsecutiveResult != RBM_NONE);

 unsigned startRegister = BitOperations::BitScanForward(limitConsecutiveResult);
 unsigned startRegister = BitScanForward(limitConsecutiveResult);

 regMaskTP registersNeededMask = (1ULL << refPosition->regCount) - 1;
 candidates |= (registersNeededMask << startRegister);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/lsra.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -794,8 +794,8 @@ class LinearScan : public LinearScanInterface
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R3 | RBM_R4 | RBM_R5);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_F0 | RBM_F1 | RBM_F2 | RBM_F16 | RBM_F17);
#elif defined(TARGET_ARM64)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
 static constexpr regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static constexpr regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
#elif defined(TARGET_X86)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_EAX | RBM_ECX | RBM_EDI);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM6 | RBM_XMM7);
Expand Down

10 changes: 5 additions & 5 deletions
src/coreclr/jit/lsraarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -180,7 +180,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 unsigned int registersNeeded,
 regMaskTP* allConsecutiveCandidates)
{
 if (BitOperations::PopCount(candidates) < registersNeeded)
 if (PopCount(candidates) < registersNeeded)
 {
 // There is no way the register demanded can be satisfied for this RefPosition
 // based on the candidates from which it can allocate a register.
Expand All@@ -205,7 +205,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(currAvailableRegs));
 regAvailableStartIndex = BitScanForward(currAvailableRegs);
 regMaskTP startMask = (1ULL << regAvailableStartIndex) - 1;

 // Mask all the bits that are processed from LSB thru regAvailableStart until the last `1`.
Expand All@@ -223,7 +223,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 }
 else
 {
 regAvailableEndIndex = BitOperations::BitScanForward(static_cast<DWORD64>(maskProcessed));
 regAvailableEndIndex = BitScanForward(maskProcessed);
 }
 regMaskTP endMask = (1ULL << regAvailableEndIndex) - 1;

Expand DownExpand Up@@ -335,7 +335,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(unprocessedRegs));
 regAvailableStartIndex = BitScanForward(unprocessedRegs);

 // For the current range, find how many registers are free vs. busy
 regMaskTP maskForCurRange = RBM_NONE;
Expand DownExpand Up@@ -370,7 +370,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 // In the given range, there are some free registers available. Calculate how many registers
 // will need spilling if this range is picked.

 int curSpillRegs = registersNeeded - BitOperations::PopCount(maskForCurRange);
 int curSpillRegs = registersNeeded - PopCount(maskForCurRange);
 if (curSpillRegs < maxSpillRegs)
 {
 consecutiveResultForBusy = 1ULL << regAvailableStartIndex;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsrabuild.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -2898,7 +2898,7 @@ void LinearScan::stressSetRandomParameterPreferences()

 // Select a random register from all possible parameter registers
 // (of the right type). Preference this parameter to that register.
 unsigned numBits = BitOperations::PopCount(*regs);
 unsigned numBits = PopCount(*regs);
 if (numBits == 0)
 {
 continue;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/regset.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -960,7 +960,7 @@ regMaskSmall genRegMaskFromCalleeSavedMask(unsigned short calleeSaveMask)
 regMaskSmall res = 0;
 for (int i = 0; i < CNT_CALLEE_SAVED; i++)
 {
 if ((calleeSaveMask & ((regMaskTP)1 << i)) != 0)
 if ((calleeSaveMask & (1 << i)) != 0)
 {
 res |= raRbmCalleeSaveOrder[i];
 }
Expand Down
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try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
Handle more than 64 registers - Part 1#101950

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 Merged

kunalspathak
merged 10 commits into

from

May 11, 2024
 Merged


Handle more than 64 registers - Part 1
#101950
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f436712

Convert regMaskTP for ARM64 to struct with single field


kunalspathak May 6, 2024
8ff7508

Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()


kunalspathak May 6, 2024
7ac4137

minor fix


kunalspathak May 6, 2024
0144cb0

review feedback


kunalspathak May 8, 2024
81b26c6

fix the TP regression from 1.5% -> 0.5%


kunalspathak May 8, 2024
261ab5d

Pass by value


kunalspathak May 8, 2024
639290c

jit format


kunalspathak May 9, 2024
28b457d

review feedback


kunalspathak May 10, 2024
0a0e61d

Remove FORCEINLINE


kunalspathak May 10, 2024
8fdbf3f

Remove setLow()


kunalspathak May 10, 2024

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9 changes: 4 additions & 5 deletions
src/coreclr/jit/codegencommon.cpp

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -3829,9 +3829,9 @@ void CodeGen::genZeroInitFltRegs(const regMaskTP& initFltRegs, const regMaskTP&

 // Iterate through float/double registers and initialize them to 0 or
 // copy from already initialized register of the same type.
 regMaskTP regMask = genRegMask(REG_FP_FIRST);
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initFltRegs)
 {
 // Do we have a float register already set to 0?
Expand DownExpand Up@@ -5732,10 +5732,9 @@ void CodeGen::genFnProlog()

 if (initRegs)
 {
 regMaskTP regMask = 0x1;

 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initRegs)
 {
 // Check if we have already zeroed this register
Expand Down

64 changes: 61 additions & 3 deletions
src/coreclr/jit/compiler.hpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -99,6 +99,33 @@ inline bool genExactlyOneBit(T value)
 return ((value != 0) && genMaxOneBit(value));
}

#ifdef TARGET_ARM64
inline regMaskTP genFindLowestBit(regMaskTP value)
{
 return regMaskTP(genFindLowestBit(value.getLow()));
}

/*****************************************************************************
 *
 * Return true if the given value has exactly zero or one bits set.
 */

inline bool genMaxOneBit(regMaskTP value)
{
 return genMaxOneBit(value.getLow());
}

/*****************************************************************************
 *
 * Return true if the given value has exactly one bit set.
 */

inline bool genExactlyOneBit(regMaskTP value)
{
 return genExactlyOneBit(value.getLow());
}
#endif

/*****************************************************************************
 *
 * Given a value that has exactly one bit set, return the position of that
Expand DownExpand Up@@ -147,6 +174,13 @@ inline unsigned genCountBits(uint64_t bits)
 return BitOperations::PopCount(bits);
}

#ifdef TARGET_ARM64
inline unsigned genCountBits(regMaskTP mask)
{
 return BitOperations::PopCount(mask.getLow());
}
#endif

/*****************************************************************************
 *
 * A rather simple routine that counts the number of bits in a given number.
Expand DownExpand Up@@ -914,11 +948,18 @@ inline regNumber genRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)genLog2(mask);
#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)genLog2(mask.getLow());

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask.getLow());

#else
 regNumber regNum = (regNumber)genLog2(mask);

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask);
#endif

 return regNum;
}
Expand All@@ -940,7 +981,8 @@ inline regNumber genFirstRegNumFromMaskAndToggle(regMaskTP& mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 mask ^= genRegMask(regNum);

 return regNum;
Expand All@@ -962,7 +1004,7 @@ inline regNumber genFirstRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 return regNum;
}
Expand DownExpand Up@@ -4463,30 +4505,46 @@ inline void* operator new[](size_t sz, Compiler* compiler, CompMemKind cmk)

inline void printRegMask(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_ALL_FMT, mask.getLow());
#else
 printf(REG_MASK_ALL_FMT, mask);
#endif
}

inline char* regMaskToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask.getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask);
#endif

 return regmask;
}

inline void printRegMaskInt(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif
}

inline char* regMaskIntToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif

 return regmask;
}
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/emit.cpp

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -3470,7 +3470,7 @@ void emitter::emitDispRegSet(regMaskTP regs)
 continue;
 }

 regs -= curReg;
 regs ^= curReg;

 if (sp)
 {
Expand DownExpand Up@@ -3828,8 +3828,8 @@ void emitter::emitDispGCRegDelta(const char* title, regMaskTP prevRegs, regMaskT
 {
 emitDispGCDeltaTitle(title);
 regMaskTP sameRegs = prevRegs & curRegs;
 regMaskTP removedRegs = prevRegs - sameRegs;
 regMaskTP addedRegs = curRegs - sameRegs;
 regMaskTP removedRegs = prevRegs ^ sameRegs;
 regMaskTP addedRegs = curRegs ^ sameRegs;
 if (removedRegs != RBM_NONE)
 {
 printf(" -");
Expand DownExpand Up@@ -8920,7 +8920,7 @@ void emitter::emitUpdateLiveGCregs(GCtype gcType, regMaskTP regs, BYTE* addr)
 emitGCregDeadUpd(reg, addr);
 }

 chg -= bit;
 chg ^= bit;
 } while (chg);

 assert(emitThisXXrefRegs == regs);
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/gcencode.cpp

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -4667,7 +4667,7 @@ void GCInfo::gcInfoRecordGCRegStateChange(GcInfoEncoder* gcInfoEncoder,
 }

 // Turn the bit we've just generated off and continue.
 regMask -= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 regMask ^= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 }
}

Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsra.cpp

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -13609,7 +13609,7 @@ regMaskTP LinearScan::RegisterSelection::select(Interval* current
 &overallLimitCandidates);
 assert(limitConsecutiveResult != RBM_NONE);

 unsigned startRegister = BitOperations::BitScanForward(limitConsecutiveResult);
 unsigned startRegister = BitScanForward(limitConsecutiveResult);

 regMaskTP registersNeededMask = (1ULL << refPosition->regCount) - 1;
 candidates |= (registersNeededMask << startRegister);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/lsra.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -794,8 +794,8 @@ class LinearScan : public LinearScanInterface
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R3 | RBM_R4 | RBM_R5);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_F0 | RBM_F1 | RBM_F2 | RBM_F16 | RBM_F17);
#elif defined(TARGET_ARM64)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
 static constexpr regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static constexpr regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
#elif defined(TARGET_X86)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_EAX | RBM_ECX | RBM_EDI);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM6 | RBM_XMM7);
Expand Down

10 changes: 5 additions & 5 deletions
src/coreclr/jit/lsraarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -180,7 +180,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 unsigned int registersNeeded,
 regMaskTP* allConsecutiveCandidates)
{
 if (BitOperations::PopCount(candidates) < registersNeeded)
 if (PopCount(candidates) < registersNeeded)
 {
 // There is no way the register demanded can be satisfied for this RefPosition
 // based on the candidates from which it can allocate a register.
Expand All@@ -205,7 +205,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(currAvailableRegs));
 regAvailableStartIndex = BitScanForward(currAvailableRegs);
 regMaskTP startMask = (1ULL << regAvailableStartIndex) - 1;

 // Mask all the bits that are processed from LSB thru regAvailableStart until the last `1`.
Expand All@@ -223,7 +223,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 }
 else
 {
 regAvailableEndIndex = BitOperations::BitScanForward(static_cast<DWORD64>(maskProcessed));
 regAvailableEndIndex = BitScanForward(maskProcessed);
 }
 regMaskTP endMask = (1ULL << regAvailableEndIndex) - 1;

Expand DownExpand Up@@ -335,7 +335,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(unprocessedRegs));
 regAvailableStartIndex = BitScanForward(unprocessedRegs);

 // For the current range, find how many registers are free vs. busy
 regMaskTP maskForCurRange = RBM_NONE;
Expand DownExpand Up@@ -370,7 +370,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 // In the given range, there are some free registers available. Calculate how many registers
 // will need spilling if this range is picked.

 int curSpillRegs = registersNeeded - BitOperations::PopCount(maskForCurRange);
 int curSpillRegs = registersNeeded - PopCount(maskForCurRange);
 if (curSpillRegs < maxSpillRegs)
 {
 consecutiveResultForBusy = 1ULL << regAvailableStartIndex;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsrabuild.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -2898,7 +2898,7 @@ void LinearScan::stressSetRandomParameterPreferences()

 // Select a random register from all possible parameter registers
 // (of the right type). Preference this parameter to that register.
 unsigned numBits = BitOperations::PopCount(*regs);
 unsigned numBits = PopCount(*regs);
 if (numBits == 0)
 {
 continue;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/regset.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -960,7 +960,7 @@ regMaskSmall genRegMaskFromCalleeSavedMask(unsigned short calleeSaveMask)
 regMaskSmall res = 0;
 for (int i = 0; i < CNT_CALLEE_SAVED; i++)
 {
 if ((calleeSaveMask & ((regMaskTP)1 << i)) != 0)
 if ((calleeSaveMask & (1 << i)) != 0)
 {
 res |= raRbmCalleeSaveOrder[i];
 }
Expand Down
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if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Universal Dark Mode - works on any site\n(function() {\n var enabled = true;\n \n function applyDarkMode() {\n if (!enabled) return;\n \n // Create style element if it doesn't exist\n var style = document.getElementById('universal-dark-mode-style');\n if (!style) {\n style = document.createElement('style');\n style.id = 'universal-dark-mode-style';\n document.head.appendChild(style);\n }\n \n // Dark mode CSS - inverts colors but preserves images/video\n style.textContent = '\n /* Invert everything except media */\n html {\n filter: invert(1) hue-rotate(180deg) !important;\n background: #1a1a2e !important;\n }\n \n /* Restore images, videos, iframes, canvas */\n img, video, iframe, canvas, svg, picture, [style*=\"background-image\"] {\n filter: invert(1) hue-rotate(180deg) !important;\n }\n \n /* Preserve specific elements that should not be inverted */\n .no-dark-mode, .no-dark-mode *,\n [data-theme=\"light\"], [data-theme=\"light\"],\n .ace_editor, .ace_editor *,\n .CodeMirror, .CodeMirror *,\n .monaco-editor, .monaco-editor *,\n .markdown-body pre, .markdown-body pre *,\n .highlight, .highlight *,\n pre code, pre code * {\n filter: none !important;\n }\n \n /* Fix common UI elements */\n .modal, .popup, .dropdown-menu, .tooltip, .popover {\n filter: invert(1) hue-rotate(180deg) !important;\n background: #2d2d44 !important;\n border-color: #444 !important;\n }\n \n /* Scrollbars */\n ::-webkit-scrollbar { background: #1a1a2e !important; }\n ::-webkit-scrollbar-thumb { background: #444 !important; }\n ::-webkit-scrollbar-thumb:hover { background: #555 !important; }\n \n /* Selection */\n ::selection { background: #4ecdc4 !important; color: #1a1a2e !important; }\n ::-moz-selection { background: #4ecdc4 !important; color: #1a1a2e !important; }\n ';\n }\n \n function removeDarkMode() {\n var style = document.getElementById('universal-dark-mode-style');\n if (style) style.remove();\n }\n \n // Toggle with Alt+Shift+D\n document.addEventListener('keydown', function(e) {\n if (e.altKey && e.shiftKey && e.key === 'D') {\n e.preventDefault();\n enabled = !enabled;\n if (enabled) {\n applyDarkMode();\n console.log('[Universal Dark Mode] Enabled');\n } else {\n removeDarkMode();\n console.log('[Universal Dark Mode] Disabled');\n }\n }\n });\n \n // Apply on load\n applyDarkMode();\n \n // Re-apply on dynamic content\n var observer = new MutationObserver(function(mutations) {\n if (enabled && !document.getElementById('universal-dark-mode-style')) {\n applyDarkMode();\n }\n });\n observer.observe(document.head, { childList: true });\n \n console.log('[Universal Dark Mode] Loaded - Press Alt+Shift+D to toggle');\n})();", "Universal Dark Mode");
}
} catch(__e) { console.warn('[Userscript:Universal Dark Mode]', __e); }
})();
})();

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 Merged

kunalspathak
merged 10 commits into

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May 11, 2024
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Handle more than 64 registers - Part 1
#101950
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f436712

Convert regMaskTP for ARM64 to struct with single field


kunalspathak May 6, 2024
8ff7508

Fix genFirstRegNumFromMaskAndToggle() and genFirstRegNumFromMask()


kunalspathak May 6, 2024
7ac4137

minor fix


kunalspathak May 6, 2024
0144cb0

review feedback


kunalspathak May 8, 2024
81b26c6

fix the TP regression from 1.5% -> 0.5%


kunalspathak May 8, 2024
261ab5d

Pass by value


kunalspathak May 8, 2024
639290c

jit format


kunalspathak May 9, 2024
28b457d

review feedback


kunalspathak May 10, 2024
0a0e61d

Remove FORCEINLINE


kunalspathak May 10, 2024
8fdbf3f

Remove setLow()


kunalspathak May 10, 2024

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9 changes: 4 additions & 5 deletions
src/coreclr/jit/codegencommon.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -3829,9 +3829,9 @@ void CodeGen::genZeroInitFltRegs(const regMaskTP& initFltRegs, const regMaskTP&

 // Iterate through float/double registers and initialize them to 0 or
 // copy from already initialized register of the same type.
 regMaskTP regMask = genRegMask(REG_FP_FIRST);
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_FP_FIRST; reg <= REG_FP_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initFltRegs)
 {
 // Do we have a float register already set to 0?
Expand DownExpand Up@@ -5732,10 +5732,9 @@ void CodeGen::genFnProlog()

 if (initRegs)
 {
 regMaskTP regMask = 0x1;

 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg), regMask <<= 1)
 for (regNumber reg = REG_INT_FIRST; reg <= REG_INT_LAST; reg = REG_NEXT(reg))
 {
 regMaskTP regMask = genRegMask(reg);
 if (regMask & initRegs)
 {
 // Check if we have already zeroed this register
Expand Down

64 changes: 61 additions & 3 deletions
src/coreclr/jit/compiler.hpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -99,6 +99,33 @@ inline bool genExactlyOneBit(T value)
 return ((value != 0) && genMaxOneBit(value));
}

#ifdef TARGET_ARM64
inline regMaskTP genFindLowestBit(regMaskTP value)
{
 return regMaskTP(genFindLowestBit(value.getLow()));
}

/*****************************************************************************
 *
 * Return true if the given value has exactly zero or one bits set.
 */

inline bool genMaxOneBit(regMaskTP value)
{
 return genMaxOneBit(value.getLow());
}

/*****************************************************************************
 *
 * Return true if the given value has exactly one bit set.
 */

inline bool genExactlyOneBit(regMaskTP value)
{
 return genExactlyOneBit(value.getLow());
}
#endif

/*****************************************************************************
 *
 * Given a value that has exactly one bit set, return the position of that
Expand DownExpand Up@@ -147,6 +174,13 @@ inline unsigned genCountBits(uint64_t bits)
 return BitOperations::PopCount(bits);
}

#ifdef TARGET_ARM64
inline unsigned genCountBits(regMaskTP mask)
{
 return BitOperations::PopCount(mask.getLow());
}
#endif

/*****************************************************************************
 *
 * A rather simple routine that counts the number of bits in a given number.
Expand DownExpand Up@@ -914,11 +948,18 @@ inline regNumber genRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)genLog2(mask);
#ifdef TARGET_ARM64
 regNumber regNum = (regNumber)genLog2(mask.getLow());

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask.getLow());

#else
 regNumber regNum = (regNumber)genLog2(mask);

 /* Make sure we got it right */
 assert(genRegMask(regNum) == mask);
#endif

 return regNum;
}
Expand All@@ -940,7 +981,8 @@ inline regNumber genFirstRegNumFromMaskAndToggle(regMaskTP& mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 mask ^= genRegMask(regNum);

 return regNum;
Expand All@@ -962,7 +1004,7 @@ inline regNumber genFirstRegNumFromMask(regMaskTP mask)

 /* Convert the mask to a register number */

 regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
 regNumber regNum = (regNumber)BitScanForward(mask);

 return regNum;
}
Expand DownExpand Up@@ -4463,30 +4505,46 @@ inline void* operator new[](size_t sz, Compiler* compiler, CompMemKind cmk)

inline void printRegMask(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_ALL_FMT, mask.getLow());
#else
 printf(REG_MASK_ALL_FMT, mask);
#endif
}

inline char* regMaskToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask.getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask);
#endif

 return regmask;
}

inline void printRegMaskInt(regMaskTP mask)
{
#ifdef TARGET_ARM64
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif
}

inline char* regMaskIntToString(regMaskTP mask, Compiler* context)
{
 const size_t cchRegMask = 24;
 char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT).getLow());
#else
 sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif

 return regmask;
}
Expand Down

8 changes: 4 additions & 4 deletions
src/coreclr/jit/emit.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -3470,7 +3470,7 @@ void emitter::emitDispRegSet(regMaskTP regs)
 continue;
 }

 regs -= curReg;
 regs ^= curReg;

 if (sp)
 {
Expand DownExpand Up@@ -3828,8 +3828,8 @@ void emitter::emitDispGCRegDelta(const char* title, regMaskTP prevRegs, regMaskT
 {
 emitDispGCDeltaTitle(title);
 regMaskTP sameRegs = prevRegs & curRegs;
 regMaskTP removedRegs = prevRegs - sameRegs;
 regMaskTP addedRegs = curRegs - sameRegs;
 regMaskTP removedRegs = prevRegs ^ sameRegs;
 regMaskTP addedRegs = curRegs ^ sameRegs;
 if (removedRegs != RBM_NONE)
 {
 printf(" -");
Expand DownExpand Up@@ -8920,7 +8920,7 @@ void emitter::emitUpdateLiveGCregs(GCtype gcType, regMaskTP regs, BYTE* addr)
 emitGCregDeadUpd(reg, addr);
 }

 chg -= bit;
 chg ^= bit;
 } while (chg);

 assert(emitThisXXrefRegs == regs);
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/gcencode.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -4667,7 +4667,7 @@ void GCInfo::gcInfoRecordGCRegStateChange(GcInfoEncoder* gcInfoEncoder,
 }

 // Turn the bit we've just generated off and continue.
 regMask -= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 regMask ^= tmpMask; // EAX,ECX,EDX,EBX,---,EBP,ESI,EDI
 }
}

Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsra.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -13609,7 +13609,7 @@ regMaskTP LinearScan::RegisterSelection::select(Interval* current
 &overallLimitCandidates);
 assert(limitConsecutiveResult != RBM_NONE);

 unsigned startRegister = BitOperations::BitScanForward(limitConsecutiveResult);
 unsigned startRegister = BitScanForward(limitConsecutiveResult);

 regMaskTP registersNeededMask = (1ULL << refPosition->regCount) - 1;
 candidates |= (registersNeededMask << startRegister);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/jit/lsra.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -794,8 +794,8 @@ class LinearScan : public LinearScanInterface
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R3 | RBM_R4 | RBM_R5);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_F0 | RBM_F1 | RBM_F2 | RBM_F16 | RBM_F17);
#elif defined(TARGET_ARM64)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
 static constexpr regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
 static constexpr regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
#elif defined(TARGET_X86)
 static const regMaskTP LsraLimitSmallIntSet = (RBM_EAX | RBM_ECX | RBM_EDI);
 static const regMaskTP LsraLimitSmallFPSet = (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM6 | RBM_XMM7);
Expand Down

10 changes: 5 additions & 5 deletions
src/coreclr/jit/lsraarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -180,7 +180,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 unsigned int registersNeeded,
 regMaskTP* allConsecutiveCandidates)
{
 if (BitOperations::PopCount(candidates) < registersNeeded)
 if (PopCount(candidates) < registersNeeded)
 {
 // There is no way the register demanded can be satisfied for this RefPosition
 // based on the candidates from which it can allocate a register.
Expand All@@ -205,7 +205,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(currAvailableRegs));
 regAvailableStartIndex = BitScanForward(currAvailableRegs);
 regMaskTP startMask = (1ULL << regAvailableStartIndex) - 1;

 // Mask all the bits that are processed from LSB thru regAvailableStart until the last `1`.
Expand All@@ -223,7 +223,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
 }
 else
 {
 regAvailableEndIndex = BitOperations::BitScanForward(static_cast<DWORD64>(maskProcessed));
 regAvailableEndIndex = BitScanForward(maskProcessed);
 }
 regMaskTP endMask = (1ULL << regAvailableEndIndex) - 1;

Expand DownExpand Up@@ -335,7 +335,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 do
 {
 // From LSB, find the first available register (bit `1`)
 regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(unprocessedRegs));
 regAvailableStartIndex = BitScanForward(unprocessedRegs);

 // For the current range, find how many registers are free vs. busy
 regMaskTP maskForCurRange = RBM_NONE;
Expand DownExpand Up@@ -370,7 +370,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
 // In the given range, there are some free registers available. Calculate how many registers
 // will need spilling if this range is picked.

 int curSpillRegs = registersNeeded - BitOperations::PopCount(maskForCurRange);
 int curSpillRegs = registersNeeded - PopCount(maskForCurRange);
 if (curSpillRegs < maxSpillRegs)
 {
 consecutiveResultForBusy = 1ULL << regAvailableStartIndex;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/lsrabuild.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -2898,7 +2898,7 @@ void LinearScan::stressSetRandomParameterPreferences()

 // Select a random register from all possible parameter registers
 // (of the right type). Preference this parameter to that register.
 unsigned numBits = BitOperations::PopCount(*regs);
 unsigned numBits = PopCount(*regs);
 if (numBits == 0)
 {
 continue;
Expand Down

2 changes: 1 addition & 1 deletion
src/coreclr/jit/regset.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -960,7 +960,7 @@ regMaskSmall genRegMaskFromCalleeSavedMask(unsigned short calleeSaveMask)
 regMaskSmall res = 0;
 for (int i = 0; i < CNT_CALLEE_SAVED; i++)
 {
 if ((calleeSaveMask & ((regMaskTP)1 << i)) != 0)
 if ((calleeSaveMask & (1 << i)) != 0)
 {
 res |= raRbmCalleeSaveOrder[i];
 }
Expand Down
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