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Has changes from #102469 and some work arounds until #102297 goes in. I will remove them from this PR once they are merged.

  • This PR basically adds a high field in regMaskTP, but do not use it.
  • Introduce a new type SingleTypeRegSet that denotes a 8-byte register set to represent registers from a single type i.e. gpr or float and in future predicated registers.
  • Updated various places in LSRA that handles transition from regMaskTP and SingleTypeRegSet. Basically, all the fields in RefPosition, Interval, RegisterSelection are updated to be SingleTypeRegSet because they can never have mixed register set.

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label May 21, 2024
@kunalspathakkunalspathak changed the title More than 64 part2 killHandle more than 64 registers - Part 3May 21, 2024
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Handle more than 64 registers - Part 3 by kunalspathak · Pull Request #102474 · dotnet/runtime · GitHub
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Has changes from #102469 and some work arounds until #102297 goes in. I will remove them from this PR once they are merged.

  • This PR basically adds a high field in regMaskTP, but do not use it.
  • Introduce a new type SingleTypeRegSet that denotes a 8-byte register set to represent registers from a single type i.e. gpr or float and in future predicated registers.
  • Updated various places in LSRA that handles transition from regMaskTP and SingleTypeRegSet. Basically, all the fields in RefPosition, Interval, RegisterSelection are updated to be SingleTypeRegSet because they can never have mixed register set.

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label May 21, 2024
@kunalspathakkunalspathak changed the title More than 64 part2 killHandle more than 64 registers - Part 3May 21, 2024
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Has changes from #102469 and some work arounds until #102297 goes in. I will remove them from this PR once they are merged.

  • This PR basically adds a high field in regMaskTP, but do not use it.
  • Introduce a new type SingleTypeRegSet that denotes a 8-byte register set to represent registers from a single type i.e. gpr or float and in future predicated registers.
  • Updated various places in LSRA that handles transition from regMaskTP and SingleTypeRegSet. Basically, all the fields in RefPosition, Interval, RegisterSelection are updated to be SingleTypeRegSet because they can never have mixed register set.

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label May 21, 2024
@kunalspathakkunalspathak changed the title More than 64 part2 killHandle more than 64 registers - Part 3May 21, 2024
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Has changes from #102469 and some work arounds until #102297 goes in. I will remove them from this PR once they are merged.

  • This PR basically adds a high field in regMaskTP, but do not use it.
  • Introduce a new type SingleTypeRegSet that denotes a 8-byte register set to represent registers from a single type i.e. gpr or float and in future predicated registers.
  • Updated various places in LSRA that handles transition from regMaskTP and SingleTypeRegSet. Basically, all the fields in RefPosition, Interval, RegisterSelection are updated to be SingleTypeRegSet because they can never have mixed register set.

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label May 21, 2024
@kunalspathakkunalspathak changed the title More than 64 part2 killHandle more than 64 registers - Part 3May 21, 2024
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Has changes from #102469 and some work arounds until #102297 goes in. I will remove them from this PR once they are merged.

  • This PR basically adds a high field in regMaskTP, but do not use it.
  • Introduce a new type SingleTypeRegSet that denotes a 8-byte register set to represent registers from a single type i.e. gpr or float and in future predicated registers.
  • Updated various places in LSRA that handles transition from regMaskTP and SingleTypeRegSet. Basically, all the fields in RefPosition, Interval, RegisterSelection are updated to be SingleTypeRegSet because they can never have mixed register set.

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label May 21, 2024
@kunalspathakkunalspathak changed the title More than 64 part2 killHandle more than 64 registers - Part 3May 21, 2024
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Has changes from #102469 and some work arounds until #102297 goes in. I will remove them from this PR once they are merged.

  • This PR basically adds a high field in regMaskTP, but do not use it.
  • Introduce a new type SingleTypeRegSet that denotes a 8-byte register set to represent registers from a single type i.e. gpr or float and in future predicated registers.
  • Updated various places in LSRA that handles transition from regMaskTP and SingleTypeRegSet. Basically, all the fields in RefPosition, Interval, RegisterSelection are updated to be SingleTypeRegSet because they can never have mixed register set.

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label May 21, 2024
@kunalspathakkunalspathak changed the title More than 64 part2 killHandle more than 64 registers - Part 3May 21, 2024
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Has changes from #102469 and some work arounds until #102297 goes in. I will remove them from this PR once they are merged.

  • This PR basically adds a high field in regMaskTP, but do not use it.
  • Introduce a new type SingleTypeRegSet that denotes a 8-byte register set to represent registers from a single type i.e. gpr or float and in future predicated registers.
  • Updated various places in LSRA that handles transition from regMaskTP and SingleTypeRegSet. Basically, all the fields in RefPosition, Interval, RegisterSelection are updated to be SingleTypeRegSet because they can never have mixed register set.

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label May 21, 2024
@kunalspathakkunalspathak changed the title More than 64 part2 killHandle more than 64 registers - Part 3May 21, 2024
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Has changes from #102469 and some work arounds until #102297 goes in. I will remove them from this PR once they are merged.

  • This PR basically adds a high field in regMaskTP, but do not use it.
  • Introduce a new type SingleTypeRegSet that denotes a 8-byte register set to represent registers from a single type i.e. gpr or float and in future predicated registers.
  • Updated various places in LSRA that handles transition from regMaskTP and SingleTypeRegSet. Basically, all the fields in RefPosition, Interval, RegisterSelection are updated to be SingleTypeRegSet because they can never have mixed register set.

@ghostghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label May 21, 2024
@kunalspathakkunalspathak changed the title More than 64 part2 killHandle more than 64 registers - Part 3May 21, 2024
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