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Add Wasm32 ISA and PackedSimd ISA - #129140
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adamperlin merged 3 commits intoJun 12, 2026
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…28 definitions for Wasm
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Pull request overview
This PR extends the CoreCLR JIT/EE instruction-set model to include a Wasm32 architecture with WasmBase, PackedSimd, and a synthetic Vector128 ISA, and wires those through the existing ThunkGenerator-driven codegen outputs (managed + native) including ReadyToRun (R2R) instruction set values. It also bumps the JIT/EE interface GUID as required when ISA definitions change.
Changes:
- Add
Wasm32 -> TARGET_WASMmapping in the thunk generator to produce correct#ifdef TARGET_WASMguards. - Define Wasm32 ISAs (
WasmBase,PackedSimd,Vector128) + implication rules inInstructionSetDesc.txt, updatingNEXT_AVAILABLE_R2R_BIT. - Regenerate/update managed and native instruction set enums/mappings (CorInfo + R2R) and bump
JITEEVersionIdentifier.
Reviewed changes
Copilot reviewed 8 out of 8 changed files in this pull request and generated 1 comment.
Show a summary per file
| File | Description |
|---|---|
| src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetGenerator.cs | Maps Wasm32 to WASM so generated native guards use TARGET_WASM. |
| src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt | Adds Wasm32 ISA definitions + implication chain and reserves R2R bits 91–92. |
| src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs | Adds Wasm32 ISA enums and implication/lookup support in the managed JIT interface model. |
| src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs | Maps Wasm32 instruction sets to R2R instruction sets (with Vector128 remaining non-R2R). |
| src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs | Adds WasmBase=91 and PackedSimd=92 to the managed R2R enum. |
| src/coreclr/inc/readytoruninstructionset.h | Adds READYTORUN_INSTRUCTION_WasmBase=91 and ..._PackedSimd=92 to the native R2R enum. |
| src/coreclr/inc/jiteeversionguid.h | Updates the JIT/EE interface GUID to reflect the ISA contract change. |
| src/coreclr/inc/corinfoinstructionset.h | Adds TARGET_WASM instruction set IDs, validation, string conversion, and R2R mapping. |
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davidwrighton
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You'll also want to adjust ConfigureInstructionSetSupport in InstructionSetHelpers.cs once you start to have an implementation, but this looks like a good starting point to get things in place to some extent.
This was referenced Jun 12, 2026
adamperlin
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Jun 12, 2026
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/ba-g previously filed failures + filed #129339 |
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Tagging subscribers to 'arch-wasm': @lewing, @pavelsavara |
adamperlin added a commit
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Jun 16, 2026
This is a follow up to #129140, so there is some duplicated diff. This PR enables `FEATURE_SIMD` and `FEATURE_HW_INTRINSICS` for `TARGET_WASM` and stubs out the minimal necessary pieces of implementation using a new `NYI_WASM_SIMD` macro and associated JitOption, `NyiWasmSimdToR2RUnsupported` to prevent crossgen failures due to the presence of intrinsics. There are a few patterns that showed up commonly which required many ifdef adjustments: 1. Assuming `!TARGET_XARCH` -> `TARGET_ARM64` if hardware intrinsics are enabled (not the case anymore with wasm) 2. Assuming `FEATURE_HW_INTRINSICS` -> `FEATURE_MASKED_HW_INTRINSICS` (not the case either for Wasm, as Wasm doesn't have any kind of mask register). Stub `HARDWARE_INTRINSIC` definitions were added for quite a few xplat `Vector128` operations even though these will not be worked on until further in the implementation plan, since the existence of these intrinsics was assumed with `FEATURE_HARDWARE_INTRINSICS` in many places. --------- Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
eiriktsarpalis pushed a commit
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Jul 15, 2026
Adds ISA definitions for `WasmBase`, `PackedSimd`, and `Vector128`. SIMD support won't be utilized yet, but this is a precursor to ongoing SIMD work.
eiriktsarpalis pushed a commit
that referenced
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Jul 15, 2026
This is a follow up to #129140, so there is some duplicated diff. This PR enables `FEATURE_SIMD` and `FEATURE_HW_INTRINSICS` for `TARGET_WASM` and stubs out the minimal necessary pieces of implementation using a new `NYI_WASM_SIMD` macro and associated JitOption, `NyiWasmSimdToR2RUnsupported` to prevent crossgen failures due to the presence of intrinsics. There are a few patterns that showed up commonly which required many ifdef adjustments: 1. Assuming `!TARGET_XARCH` -> `TARGET_ARM64` if hardware intrinsics are enabled (not the case anymore with wasm) 2. Assuming `FEATURE_HW_INTRINSICS` -> `FEATURE_MASKED_HW_INTRINSICS` (not the case either for Wasm, as Wasm doesn't have any kind of mask register). Stub `HARDWARE_INTRINSIC` definitions were added for quite a few xplat `Vector128` operations even though these will not be worked on until further in the implementation plan, since the existence of these intrinsics was assumed with `FEATURE_HARDWARE_INTRINSICS` in many places. --------- Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
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Adds ISA definitions for
WasmBase,PackedSimd, andVector128. SIMD support won't be utilized yet, but this is a precursor to ongoing SIMD work.