[Arm64] Implement Store Hardware Intrinsic#33535

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Merged
echesakov merged 12 commits into from
Mar 19, 2020
Merged

[Arm64] Implement Store Hardware Intrinsic #33535

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80c7ad8
Put FusedMultiplyAdd and FusedMultiplySubtract after Divide in AdvSim…
echesakov Mar 11, 2020
9b61408
Add Store in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
echesakov Mar 11, 2020
0d56a72
Add Store in hwintrinsiclistarm64.h
echesakov Mar 11, 2020
09580d0
Add Store in CodeGen::genHWIntrinsic() in hwintrinsiccodegenarm64.cpp
echesakov Mar 12, 2020
feed1b7
lookupSimdSize for Category_MemoryStore should return second argument…
echesakov Mar 12, 2020
cb4ffdd
Update System.Runtime.Intrinsics.Experimental.cs
echesakov Mar 11, 2020
d1afc1e
Add StoreUnOpTest.template
echesakov Mar 11, 2020
3e1ec01
Add Store in GenerateTests.csx
echesakov Mar 12, 2020
9ec704d
Update AdvSimd/
echesakov Mar 12, 2020
c8d6cc4
Address Brian's feedback on GitHub for #33461
echesakov Mar 14, 2020
25fd0d8
Partly address Bruce's feedback on GitHub for #33461
echesakov Mar 14, 2020
77d4077
Revert "lookupSimdSize for Category_MemoryStore should return second …
echesakov Mar 17, 2020
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12 changes: 6 additions & 6 deletions src/coreclr/src/jit/codegenarm64.cpp
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Original file line numberDiff line numberDiff line change
Expand Up@@ -5230,7 +5230,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
//
// Loads to /Stores from one, two, three, or four SIMD&FP registers
// Loads to and Stores from one, two, three, or four SIMD&FP registers
//

genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5413,7 +5413,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
//
// Loads to /Stores from one, two, three, or four SIMD&FP registers
// Loads to and Stores from one, two, three, or four SIMD&FP registers
//

genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5596,7 +5596,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
//
// Loads to /Stores from one, two, three, or four SIMD&FP registers
// Loads to and Stores from one, two, three, or four SIMD&FP registers
//

genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5779,7 +5779,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
//
// Loads to /Stores from one, two, three, or four SIMD&FP registers
// Loads to and Stores from one, two, three, or four SIMD&FP registers
//

genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5836,7 +5836,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
//
// Loads to /Stores from one, two, three, or four SIMD&FP registers
// Loads to and Stores from one, two, three, or four SIMD&FP registers
//

genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5893,7 +5893,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
//
// Loads to /Stores from one, two, three, or four SIMD&FP registers
// Loads to and Stores from one, two, three, or four SIMD&FP registers
//

genDefineTempLabel(genCreateTempLabel());
Expand Down
16 changes: 8 additions & 8 deletions src/coreclr/src/jit/emitarm64.cpp
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Original file line numberDiff line numberDiff line change
Expand Up@@ -229,8 +229,8 @@ void emitter::emitInsSanityCheck(instrDesc* id)

case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
assert(isVectorRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2())); // SP
if (insOptsAnyArrangement(id->idInsOpt()))
Expand DownExpand Up@@ -959,8 +959,8 @@ bool emitter::emitInsMayWriteToGCReg(instrDesc* id)
case IF_LS_2C: // LS_2C .X.......X.iiiii iiiiP.nnnnnttttt Rt Rn imm(-256..+255) pre/post inc
case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
case IF_LS_3A: // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
case IF_LS_3B: // LS_3B X............... .aaaaannnnnttttt Rt Ra Rn
case IF_LS_3C: // LS_3C X.........iiiiii iaaaaannnnnttttt Rt Ra Rn imm(im7,sh)
Expand DownExpand Up@@ -9762,8 +9762,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
dst += emitOutput_Instr(dst, code);
break;

case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
elemsize = id->idOpSize();
index = id->idSmallCns();
code = emitInsCode(ins, fmt);
Expand DownExpand Up@@ -11645,8 +11645,8 @@ void emitter::emitDispIns(
}
break;

case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
registerListSize = insGetLoadStoreRegisterListSize(id->idIns());
elemsize = id->idOpSize();
emitDispVectorElemList(id->idReg1(), registerListSize, elemsize, id->idSmallCns(), true);
Expand Down
4 changes: 2 additions & 2 deletions src/coreclr/src/jit/emitfmtsarm64.h
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Original file line numberDiff line numberDiff line change
Expand Up@@ -138,8 +138,8 @@ IF_DEF(LS_2D, IS_NONE, NONE) // LS_2D .Q.............. ....ssnnnnnttttt V
// Load single structure and replicate base register
IF_DEF(LS_2E, IS_NONE, NONE) // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn Load/Store multiple structures post-indexed by an immediate
// Load single structure and replicate post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_3A, IS_NONE, NONE) // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
IF_DEF(LS_3B, IS_NONE, NONE) // LS_3B X............... .aaaaannnnnddddd Rd Ra Rn
IF_DEF(LS_3C, IS_NONE, NONE) // LS_3C X.........iiiiii iaaaaannnnnddddd Rd Ra Rn imm(im7,sh)
Expand Down
5 changes: 2 additions & 3 deletions src/coreclr/src/jit/hwintrinsic.cpp
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Original file line numberDiff line numberDiff line change
Expand Up@@ -61,12 +61,11 @@ var_types Compiler::getBaseTypeFromArgIfNeeded(NamedIntrinsic intrinsic,
{
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);

if (category == HW_Category_MemoryStore || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) ||
HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) || HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
{
CORINFO_ARG_LIST_HANDLE arg = sig->args;

if ((category == HW_Category_MemoryStore) || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
{
arg = info.compCompHnd->getArgNext(arg);
}
Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp
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Original file line numberDiff line numberDiff line change
Expand Up@@ -301,6 +301,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, op1Reg);
break;

case NI_AdvSimd_Store:
GetEmitter()->emitIns_R_R(ins, emitSize, op2Reg, op1Reg, opt);
break;

default:
unreached();
}
Expand Down
1 change: 1 addition & 0 deletions src/coreclr/src/jit/hwintrinsiclistarm64.h
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Expand Up@@ -97,6 +97,7 @@ HARDWARE_INTRINSIC(AdvSimd, Or, -
HARDWARE_INTRINSIC(AdvSimd, OrNot, -1, -1, 2, {INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, PopCount, -1, -1, 1, {INS_cnt, INS_cnt, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SqrtScalar, -1, 8, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_fsqrt, INS_fsqrt}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Store, -1, -1, 2, {INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1}, HW_Category_MemoryStore, HW_Flag_NoRMWSemantics|HW_Flag_UnfixedSIMDSize|HW_Flag_SpecialCodeGen|HW_Flag_BaseTypeFromSecondArg)
HARDWARE_INTRINSIC(AdvSimd, Subtract, -1, -1, 2, {INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_fsub, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SubtractScalar, -1, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sub, INS_sub, INS_fsub, INS_fsub}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Xor, -1, -1, 2, {INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize|HW_Flag_Commutative)
Expand Down
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[Arm64] Implement Store Hardware Intrinsic#33535

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 Merged

echesakov
merged 12 commits into

from

Mar 19, 2020
 Merged


[Arm64] Implement Store Hardware Intrinsic
#33535
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80c7ad8

Put FusedMultiplyAdd and FusedMultiplySubtract after Divide in AdvSim…


echesakov Mar 11, 2020
9b61408

Add Store in AdvSimd.cs AdvSimd.PlatformNotSupported.cs


echesakov Mar 11, 2020
0d56a72

Add Store in hwintrinsiclistarm64.h


echesakov Mar 11, 2020
09580d0

Add Store in CodeGen::genHWIntrinsic() in hwintrinsiccodegenarm64.cpp


echesakov Mar 12, 2020
feed1b7

lookupSimdSize for Category_MemoryStore should return second argument…


echesakov Mar 12, 2020
cb4ffdd

Update System.Runtime.Intrinsics.Experimental.cs


echesakov Mar 11, 2020
d1afc1e

Add StoreUnOpTest.template


echesakov Mar 11, 2020
3e1ec01

Add Store in GenerateTests.csx


echesakov Mar 12, 2020
9ec704d

Update AdvSimd/


echesakov Mar 12, 2020
c8d6cc4

Address Brian's feedback on GitHub for #33461


echesakov Mar 14, 2020
25fd0d8

Partly address Bruce's feedback on GitHub for #33461


echesakov Mar 14, 2020
77d4077

Revert "lookupSimdSize for Category_MemoryStore should return second …


echesakov Mar 17, 2020

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12 changes: 6 additions & 6 deletions
src/coreclr/src/jit/codegenarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -5230,7 +5230,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5413,7 +5413,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5596,7 +5596,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5779,7 +5779,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5836,7 +5836,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5893,7 +5893,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand Down

16 changes: 8 additions & 8 deletions
src/coreclr/src/jit/emitarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -229,8 +229,8 @@ void emitter::emitInsSanityCheck(instrDesc* id)

 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 assert(isVectorRegister(id->idReg1()));
 assert(isIntegerRegister(id->idReg2())); // SP
 if (insOptsAnyArrangement(id->idInsOpt()))
Expand DownExpand Up@@ -959,8 +959,8 @@ bool emitter::emitInsMayWriteToGCReg(instrDesc* id)
 case IF_LS_2C: // LS_2C .X.......X.iiiii iiiiP.nnnnnttttt Rt Rn imm(-256..+255) pre/post inc
 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_3A: // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
 case IF_LS_3B: // LS_3B X............... .aaaaannnnnttttt Rt Ra Rn
 case IF_LS_3C: // LS_3C X.........iiiiii iaaaaannnnnttttt Rt Ra Rn imm(im7,sh)
Expand DownExpand Up@@ -9762,8 +9762,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
 dst += emitOutput_Instr(dst, code);
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 elemsize = id->idOpSize();
 index = id->idSmallCns();
 code = emitInsCode(ins, fmt);
Expand DownExpand Up@@ -11645,8 +11645,8 @@ void emitter::emitDispIns(
 }
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 registerListSize = insGetLoadStoreRegisterListSize(id->idIns());
 elemsize = id->idOpSize();
 emitDispVectorElemList(id->idReg1(), registerListSize, elemsize, id->idSmallCns(), true);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/src/jit/emitfmtsarm64.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -138,8 +138,8 @@ IF_DEF(LS_2D, IS_NONE, NONE) // LS_2D .Q.............. ....ssnnnnnttttt V
 // Load single structure and replicate base register
IF_DEF(LS_2E, IS_NONE, NONE) // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn Load/Store multiple structures post-indexed by an immediate
 // Load single structure and replicate post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_3A, IS_NONE, NONE) // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
IF_DEF(LS_3B, IS_NONE, NONE) // LS_3B X............... .aaaaannnnnddddd Rd Ra Rn
IF_DEF(LS_3C, IS_NONE, NONE) // LS_3C X.........iiiiii iaaaaannnnnddddd Rd Ra Rn imm(im7,sh)
Expand Down

5 changes: 2 additions & 3 deletions
src/coreclr/src/jit/hwintrinsic.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -61,12 +61,11 @@ var_types Compiler::getBaseTypeFromArgIfNeeded(NamedIntrinsic intrinsic,
{
 HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);

 if (category == HW_Category_MemoryStore || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) ||
 HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) || HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 {
 CORINFO_ARG_LIST_HANDLE arg = sig->args;

 if ((category == HW_Category_MemoryStore) || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 {
 arg = info.compCompHnd->getArgNext(arg);
 }
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -301,6 +301,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
 GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, op1Reg);
 break;

 case NI_AdvSimd_Store:
 GetEmitter()->emitIns_R_R(ins, emitSize, op2Reg, op1Reg, opt);
 break;

 default:
 unreached();
 }
Expand Down

1 change: 1 addition & 0 deletions
src/coreclr/src/jit/hwintrinsiclistarm64.h

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -97,6 +97,7 @@ HARDWARE_INTRINSIC(AdvSimd, Or, -
HARDWARE_INTRINSIC(AdvSimd, OrNot, -1, -1, 2, {INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, PopCount, -1, -1, 1, {INS_cnt, INS_cnt, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SqrtScalar, -1, 8, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_fsqrt, INS_fsqrt}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Store, -1, -1, 2, {INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1}, HW_Category_MemoryStore, HW_Flag_NoRMWSemantics|HW_Flag_UnfixedSIMDSize|HW_Flag_SpecialCodeGen|HW_Flag_BaseTypeFromSecondArg)
HARDWARE_INTRINSIC(AdvSimd, Subtract, -1, -1, 2, {INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_fsub, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SubtractScalar, -1, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sub, INS_sub, INS_fsub, INS_fsub}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Xor, -1, -1, 2, {INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize|HW_Flag_Commutative)
Expand Down
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Skip to content
[Arm64] Implement Store Hardware Intrinsic#33535

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 Merged

echesakov
merged 12 commits into

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Mar 19, 2020
 Merged


[Arm64] Implement Store Hardware Intrinsic
#33535
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80c7ad8

Put FusedMultiplyAdd and FusedMultiplySubtract after Divide in AdvSim…


echesakov Mar 11, 2020
9b61408

Add Store in AdvSimd.cs AdvSimd.PlatformNotSupported.cs


echesakov Mar 11, 2020
0d56a72

Add Store in hwintrinsiclistarm64.h


echesakov Mar 11, 2020
09580d0

Add Store in CodeGen::genHWIntrinsic() in hwintrinsiccodegenarm64.cpp


echesakov Mar 12, 2020
feed1b7

lookupSimdSize for Category_MemoryStore should return second argument…


echesakov Mar 12, 2020
cb4ffdd

Update System.Runtime.Intrinsics.Experimental.cs


echesakov Mar 11, 2020
d1afc1e

Add StoreUnOpTest.template


echesakov Mar 11, 2020
3e1ec01

Add Store in GenerateTests.csx


echesakov Mar 12, 2020
9ec704d

Update AdvSimd/


echesakov Mar 12, 2020
c8d6cc4

Address Brian's feedback on GitHub for #33461


echesakov Mar 14, 2020
25fd0d8

Partly address Bruce's feedback on GitHub for #33461


echesakov Mar 14, 2020
77d4077

Revert "lookupSimdSize for Category_MemoryStore should return second …


echesakov Mar 17, 2020

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12 changes: 6 additions & 6 deletions
src/coreclr/src/jit/codegenarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -5230,7 +5230,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5413,7 +5413,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5596,7 +5596,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5779,7 +5779,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5836,7 +5836,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5893,7 +5893,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand Down

16 changes: 8 additions & 8 deletions
src/coreclr/src/jit/emitarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -229,8 +229,8 @@ void emitter::emitInsSanityCheck(instrDesc* id)

 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 assert(isVectorRegister(id->idReg1()));
 assert(isIntegerRegister(id->idReg2())); // SP
 if (insOptsAnyArrangement(id->idInsOpt()))
Expand DownExpand Up@@ -959,8 +959,8 @@ bool emitter::emitInsMayWriteToGCReg(instrDesc* id)
 case IF_LS_2C: // LS_2C .X.......X.iiiii iiiiP.nnnnnttttt Rt Rn imm(-256..+255) pre/post inc
 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_3A: // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
 case IF_LS_3B: // LS_3B X............... .aaaaannnnnttttt Rt Ra Rn
 case IF_LS_3C: // LS_3C X.........iiiiii iaaaaannnnnttttt Rt Ra Rn imm(im7,sh)
Expand DownExpand Up@@ -9762,8 +9762,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
 dst += emitOutput_Instr(dst, code);
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 elemsize = id->idOpSize();
 index = id->idSmallCns();
 code = emitInsCode(ins, fmt);
Expand DownExpand Up@@ -11645,8 +11645,8 @@ void emitter::emitDispIns(
 }
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 registerListSize = insGetLoadStoreRegisterListSize(id->idIns());
 elemsize = id->idOpSize();
 emitDispVectorElemList(id->idReg1(), registerListSize, elemsize, id->idSmallCns(), true);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/src/jit/emitfmtsarm64.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -138,8 +138,8 @@ IF_DEF(LS_2D, IS_NONE, NONE) // LS_2D .Q.............. ....ssnnnnnttttt V
 // Load single structure and replicate base register
IF_DEF(LS_2E, IS_NONE, NONE) // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn Load/Store multiple structures post-indexed by an immediate
 // Load single structure and replicate post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_3A, IS_NONE, NONE) // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
IF_DEF(LS_3B, IS_NONE, NONE) // LS_3B X............... .aaaaannnnnddddd Rd Ra Rn
IF_DEF(LS_3C, IS_NONE, NONE) // LS_3C X.........iiiiii iaaaaannnnnddddd Rd Ra Rn imm(im7,sh)
Expand Down

5 changes: 2 additions & 3 deletions
src/coreclr/src/jit/hwintrinsic.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -61,12 +61,11 @@ var_types Compiler::getBaseTypeFromArgIfNeeded(NamedIntrinsic intrinsic,
{
 HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);

 if (category == HW_Category_MemoryStore || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) ||
 HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) || HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 {
 CORINFO_ARG_LIST_HANDLE arg = sig->args;

 if ((category == HW_Category_MemoryStore) || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 {
 arg = info.compCompHnd->getArgNext(arg);
 }
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -301,6 +301,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
 GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, op1Reg);
 break;

 case NI_AdvSimd_Store:
 GetEmitter()->emitIns_R_R(ins, emitSize, op2Reg, op1Reg, opt);
 break;

 default:
 unreached();
 }
Expand Down

1 change: 1 addition & 0 deletions
src/coreclr/src/jit/hwintrinsiclistarm64.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -97,6 +97,7 @@ HARDWARE_INTRINSIC(AdvSimd, Or, -
HARDWARE_INTRINSIC(AdvSimd, OrNot, -1, -1, 2, {INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, PopCount, -1, -1, 1, {INS_cnt, INS_cnt, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SqrtScalar, -1, 8, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_fsqrt, INS_fsqrt}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Store, -1, -1, 2, {INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1}, HW_Category_MemoryStore, HW_Flag_NoRMWSemantics|HW_Flag_UnfixedSIMDSize|HW_Flag_SpecialCodeGen|HW_Flag_BaseTypeFromSecondArg)
HARDWARE_INTRINSIC(AdvSimd, Subtract, -1, -1, 2, {INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_fsub, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SubtractScalar, -1, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sub, INS_sub, INS_fsub, INS_fsub}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Xor, -1, -1, 2, {INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize|HW_Flag_Commutative)
Expand Down
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if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Highlight search terms from Google/DuckDuckGo/Bing referrer\n(function() {\n var ref = document.referrer;\n var terms = [];\n \n if (ref.includes('google.com') || ref.includes('duckduckgo.com') || ref.includes('bing.com')) {\n var url = new URL(ref);\n var q = url.searchParams.get('q') || url.searchParams.get('p');\n if (q) {\n terms = q.split(/\\s+/).filter(function(t) { return t.length > 2; });\n }\n }\n \n if (terms.length === 0) return;\n \n var style = document.createElement('style');\n style.textContent = '.userscript-highlight { background: #fbbf24; color: #1a1a2e; padding: 1px 3px; border-radius: 2px; }';\n document.head.appendChild(style);\n \n function highlight(node) {\n if (node.nodeType === 3) { // text node\n var text = node.textContent;\n var found = false;\n terms.forEach(function(term) {\n var regex = new RegExp('(' + term.replace(/[.*+?^${}()|[\\]\\\\]/g, '\\\\') + ')', 'gi');\n if (regex.test(text)) {\n found = true;\n var frag = document.createDocumentFragment();\n var parts = text.split(regex);\n parts.forEach(function(part, i) {\n if (i % 2 === 0) {\n frag.appendChild(document.createTextNode(part));\n } else {\n var span = document.createElement('span');\n span.className = 'userscript-highlight';\n span.textContent = part;\n frag.appendChild(span);\n }\n });\n node.parentNode.replaceChild(frag, node);\n }\n });\n } else if (node.nodeType === 1 && node.childNodes) { // element\n var skipTags = ['SCRIPT', 'STYLE', 'NOSCRIPT', 'TEXTAREA', 'INPUT', 'SELECT'];\n if (!skipTags.includes(node.tagName)) {\n Array.from(node.childNodes).forEach(highlight);\n }\n }\n }\n \n highlight(document.body);\n \n // Re-highlight on dynamic content\n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1 || node.nodeType === 3) highlight(node);\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Highlight Search Terms");
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var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
[Arm64] Implement Store Hardware Intrinsic#33535

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 Merged

echesakov
merged 12 commits into

from

Mar 19, 2020
 Merged


[Arm64] Implement Store Hardware Intrinsic
#33535
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80c7ad8

Put FusedMultiplyAdd and FusedMultiplySubtract after Divide in AdvSim…


echesakov Mar 11, 2020
9b61408

Add Store in AdvSimd.cs AdvSimd.PlatformNotSupported.cs


echesakov Mar 11, 2020
0d56a72

Add Store in hwintrinsiclistarm64.h


echesakov Mar 11, 2020
09580d0

Add Store in CodeGen::genHWIntrinsic() in hwintrinsiccodegenarm64.cpp


echesakov Mar 12, 2020
feed1b7

lookupSimdSize for Category_MemoryStore should return second argument…


echesakov Mar 12, 2020
cb4ffdd

Update System.Runtime.Intrinsics.Experimental.cs


echesakov Mar 11, 2020
d1afc1e

Add StoreUnOpTest.template


echesakov Mar 11, 2020
3e1ec01

Add Store in GenerateTests.csx


echesakov Mar 12, 2020
9ec704d

Update AdvSimd/


echesakov Mar 12, 2020
c8d6cc4

Address Brian's feedback on GitHub for #33461


echesakov Mar 14, 2020
25fd0d8

Partly address Bruce's feedback on GitHub for #33461


echesakov Mar 14, 2020
77d4077

Revert "lookupSimdSize for Category_MemoryStore should return second …


echesakov Mar 17, 2020

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12 changes: 6 additions & 6 deletions
src/coreclr/src/jit/codegenarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -5230,7 +5230,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5413,7 +5413,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5596,7 +5596,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5779,7 +5779,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5836,7 +5836,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5893,7 +5893,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand Down

16 changes: 8 additions & 8 deletions
src/coreclr/src/jit/emitarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -229,8 +229,8 @@ void emitter::emitInsSanityCheck(instrDesc* id)

 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 assert(isVectorRegister(id->idReg1()));
 assert(isIntegerRegister(id->idReg2())); // SP
 if (insOptsAnyArrangement(id->idInsOpt()))
Expand DownExpand Up@@ -959,8 +959,8 @@ bool emitter::emitInsMayWriteToGCReg(instrDesc* id)
 case IF_LS_2C: // LS_2C .X.......X.iiiii iiiiP.nnnnnttttt Rt Rn imm(-256..+255) pre/post inc
 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_3A: // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
 case IF_LS_3B: // LS_3B X............... .aaaaannnnnttttt Rt Ra Rn
 case IF_LS_3C: // LS_3C X.........iiiiii iaaaaannnnnttttt Rt Ra Rn imm(im7,sh)
Expand DownExpand Up@@ -9762,8 +9762,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
 dst += emitOutput_Instr(dst, code);
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 elemsize = id->idOpSize();
 index = id->idSmallCns();
 code = emitInsCode(ins, fmt);
Expand DownExpand Up@@ -11645,8 +11645,8 @@ void emitter::emitDispIns(
 }
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 registerListSize = insGetLoadStoreRegisterListSize(id->idIns());
 elemsize = id->idOpSize();
 emitDispVectorElemList(id->idReg1(), registerListSize, elemsize, id->idSmallCns(), true);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/src/jit/emitfmtsarm64.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -138,8 +138,8 @@ IF_DEF(LS_2D, IS_NONE, NONE) // LS_2D .Q.............. ....ssnnnnnttttt V
 // Load single structure and replicate base register
IF_DEF(LS_2E, IS_NONE, NONE) // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn Load/Store multiple structures post-indexed by an immediate
 // Load single structure and replicate post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_3A, IS_NONE, NONE) // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
IF_DEF(LS_3B, IS_NONE, NONE) // LS_3B X............... .aaaaannnnnddddd Rd Ra Rn
IF_DEF(LS_3C, IS_NONE, NONE) // LS_3C X.........iiiiii iaaaaannnnnddddd Rd Ra Rn imm(im7,sh)
Expand Down

5 changes: 2 additions & 3 deletions
src/coreclr/src/jit/hwintrinsic.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -61,12 +61,11 @@ var_types Compiler::getBaseTypeFromArgIfNeeded(NamedIntrinsic intrinsic,
{
 HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);

 if (category == HW_Category_MemoryStore || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) ||
 HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) || HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 {
 CORINFO_ARG_LIST_HANDLE arg = sig->args;

 if ((category == HW_Category_MemoryStore) || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 {
 arg = info.compCompHnd->getArgNext(arg);
 }
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -301,6 +301,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
 GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, op1Reg);
 break;

 case NI_AdvSimd_Store:
 GetEmitter()->emitIns_R_R(ins, emitSize, op2Reg, op1Reg, opt);
 break;

 default:
 unreached();
 }
Expand Down

1 change: 1 addition & 0 deletions
src/coreclr/src/jit/hwintrinsiclistarm64.h

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -97,6 +97,7 @@ HARDWARE_INTRINSIC(AdvSimd, Or, -
HARDWARE_INTRINSIC(AdvSimd, OrNot, -1, -1, 2, {INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, PopCount, -1, -1, 1, {INS_cnt, INS_cnt, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SqrtScalar, -1, 8, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_fsqrt, INS_fsqrt}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Store, -1, -1, 2, {INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1}, HW_Category_MemoryStore, HW_Flag_NoRMWSemantics|HW_Flag_UnfixedSIMDSize|HW_Flag_SpecialCodeGen|HW_Flag_BaseTypeFromSecondArg)
HARDWARE_INTRINSIC(AdvSimd, Subtract, -1, -1, 2, {INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_fsub, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SubtractScalar, -1, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sub, INS_sub, INS_fsub, INS_fsub}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Xor, -1, -1, 2, {INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize|HW_Flag_Commutative)
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Strip utm_, fbclid, gclid, etc. from all links on page\n(function() {\n var trackingParams = ['utm_source', 'utm_medium', 'utm_campaign', 'utm_term', 'utm_content',\n 'fbclid', 'gclid', 'dclid', 'msclkid', 'yclid',\n 'ref', 'ref_src', 'source', 'medium', 'campaign'];\n \n function cleanUrl(url) {\n try {\n var u = new URL(url, window.location.origin);\n var changed = false;\n trackingParams.forEach(function(p) {\n if (u.searchParams.has(p)) {\n u.searchParams.delete(p);\n changed = true;\n }\n });\n return changed ? u.toString() : url;\n } catch (e) {\n return url;\n }\n }\n \n function cleanLinks() {\n document.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n \n cleanLinks();\n \n var observer = new MutationObserver(function(mutations) {\n mutations.forEach(function(m) {\n m.addedNodes.forEach(function(node) {\n if (node.nodeType === 1) {\n if (node.tagName === 'A') cleanLinks();\n node.querySelectorAll('a[href]').forEach(function(a) {\n var clean = cleanUrl(a.href);\n if (clean !== a.href) a.href = clean;\n });\n }\n });\n });\n });\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "Remove Tracking Parameters from Links");
}
} catch(__e) { console.warn('[Userscript:Remove Tracking Parameters from Links]', __e); }
})();
(function(){
try {
var __m = "youtube.com";
var __re = new RegExp('^' + "youtube\\.com" + '

Skip to content
[Arm64] Implement Store Hardware Intrinsic#33535

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 Merged

echesakov
merged 12 commits into

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Mar 19, 2020
 Merged


[Arm64] Implement Store Hardware Intrinsic
#33535
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80c7ad8

Put FusedMultiplyAdd and FusedMultiplySubtract after Divide in AdvSim…


echesakov Mar 11, 2020
9b61408

Add Store in AdvSimd.cs AdvSimd.PlatformNotSupported.cs


echesakov Mar 11, 2020
0d56a72

Add Store in hwintrinsiclistarm64.h


echesakov Mar 11, 2020
09580d0

Add Store in CodeGen::genHWIntrinsic() in hwintrinsiccodegenarm64.cpp


echesakov Mar 12, 2020
feed1b7

lookupSimdSize for Category_MemoryStore should return second argument…


echesakov Mar 12, 2020
cb4ffdd

Update System.Runtime.Intrinsics.Experimental.cs


echesakov Mar 11, 2020
d1afc1e

Add StoreUnOpTest.template


echesakov Mar 11, 2020
3e1ec01

Add Store in GenerateTests.csx


echesakov Mar 12, 2020
9ec704d

Update AdvSimd/


echesakov Mar 12, 2020
c8d6cc4

Address Brian's feedback on GitHub for #33461


echesakov Mar 14, 2020
25fd0d8

Partly address Bruce's feedback on GitHub for #33461


echesakov Mar 14, 2020
77d4077

Revert "lookupSimdSize for Category_MemoryStore should return second …


echesakov Mar 17, 2020

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12 changes: 6 additions & 6 deletions
src/coreclr/src/jit/codegenarm64.cpp

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -5230,7 +5230,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5413,7 +5413,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5596,7 +5596,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5779,7 +5779,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5836,7 +5836,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5893,7 +5893,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand Down

16 changes: 8 additions & 8 deletions
src/coreclr/src/jit/emitarm64.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -229,8 +229,8 @@ void emitter::emitInsSanityCheck(instrDesc* id)

 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 assert(isVectorRegister(id->idReg1()));
 assert(isIntegerRegister(id->idReg2())); // SP
 if (insOptsAnyArrangement(id->idInsOpt()))
Expand DownExpand Up@@ -959,8 +959,8 @@ bool emitter::emitInsMayWriteToGCReg(instrDesc* id)
 case IF_LS_2C: // LS_2C .X.......X.iiiii iiiiP.nnnnnttttt Rt Rn imm(-256..+255) pre/post inc
 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_3A: // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
 case IF_LS_3B: // LS_3B X............... .aaaaannnnnttttt Rt Ra Rn
 case IF_LS_3C: // LS_3C X.........iiiiii iaaaaannnnnttttt Rt Ra Rn imm(im7,sh)
Expand DownExpand Up@@ -9762,8 +9762,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
 dst += emitOutput_Instr(dst, code);
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 elemsize = id->idOpSize();
 index = id->idSmallCns();
 code = emitInsCode(ins, fmt);
Expand DownExpand Up@@ -11645,8 +11645,8 @@ void emitter::emitDispIns(
 }
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 registerListSize = insGetLoadStoreRegisterListSize(id->idIns());
 elemsize = id->idOpSize();
 emitDispVectorElemList(id->idReg1(), registerListSize, elemsize, id->idSmallCns(), true);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/src/jit/emitfmtsarm64.h

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -138,8 +138,8 @@ IF_DEF(LS_2D, IS_NONE, NONE) // LS_2D .Q.............. ....ssnnnnnttttt V
 // Load single structure and replicate base register
IF_DEF(LS_2E, IS_NONE, NONE) // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn Load/Store multiple structures post-indexed by an immediate
 // Load single structure and replicate post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_3A, IS_NONE, NONE) // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
IF_DEF(LS_3B, IS_NONE, NONE) // LS_3B X............... .aaaaannnnnddddd Rd Ra Rn
IF_DEF(LS_3C, IS_NONE, NONE) // LS_3C X.........iiiiii iaaaaannnnnddddd Rd Ra Rn imm(im7,sh)
Expand Down

5 changes: 2 additions & 3 deletions
src/coreclr/src/jit/hwintrinsic.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -61,12 +61,11 @@ var_types Compiler::getBaseTypeFromArgIfNeeded(NamedIntrinsic intrinsic,
{
 HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);

 if (category == HW_Category_MemoryStore || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) ||
 HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) || HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 {
 CORINFO_ARG_LIST_HANDLE arg = sig->args;

 if ((category == HW_Category_MemoryStore) || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 {
 arg = info.compCompHnd->getArgNext(arg);
 }
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -301,6 +301,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
 GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, op1Reg);
 break;

 case NI_AdvSimd_Store:
 GetEmitter()->emitIns_R_R(ins, emitSize, op2Reg, op1Reg, opt);
 break;

 default:
 unreached();
 }
Expand Down

1 change: 1 addition & 0 deletions
src/coreclr/src/jit/hwintrinsiclistarm64.h

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -97,6 +97,7 @@ HARDWARE_INTRINSIC(AdvSimd, Or, -
HARDWARE_INTRINSIC(AdvSimd, OrNot, -1, -1, 2, {INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, PopCount, -1, -1, 1, {INS_cnt, INS_cnt, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SqrtScalar, -1, 8, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_fsqrt, INS_fsqrt}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Store, -1, -1, 2, {INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1}, HW_Category_MemoryStore, HW_Flag_NoRMWSemantics|HW_Flag_UnfixedSIMDSize|HW_Flag_SpecialCodeGen|HW_Flag_BaseTypeFromSecondArg)
HARDWARE_INTRINSIC(AdvSimd, Subtract, -1, -1, 2, {INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_fsub, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SubtractScalar, -1, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sub, INS_sub, INS_fsub, INS_fsub}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Xor, -1, -1, 2, {INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize|HW_Flag_Commutative)
Expand Down
Loading

, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Auto-enable theater mode on YouTube\n(function() {\n function tryTheater() {\n var btn = document.querySelector('button[aria-label=\"Theater mode\"], ytd-player #player button[title=\"Theater mode\"]');\n if (btn && !btn.classList.contains('activated')) {\n btn.click();\n }\n }\n \n // Try immediately\n tryTheater();\n \n // Try after navigation (SPA)\n var lastUrl = location.href;\n setInterval(function() {\n if (location.href !== lastUrl) {\n lastUrl = location.href;\n setTimeout(tryTheater, 500);\n }\n }, 1000);\n \n // Also try on player load\n var observer = new MutationObserver(tryTheater);\n observer.observe(document.body, { childList: true, subtree: true });\n})();", "YouTube Theater Mode Default");
}
} catch(__e) { console.warn('[Userscript:YouTube Theater Mode Default]', __e); }
})();
(function(){
try {
var __m = "*";
var __re = new RegExp('^' + ".*" + '

Skip to content
[Arm64] Implement Store Hardware Intrinsic#33535

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

 Sign up for GitHub

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privacy statement. We’ll occasionally send you account related emails.

Already on GitHub?
Sign in
to your account

 Merged

echesakov
merged 12 commits into

from

Mar 19, 2020
 Merged


[Arm64] Implement Store Hardware Intrinsic
#33535
Show file tree
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Commits

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12 commits


Select commit
Hold shift + click to select a range
80c7ad8

Put FusedMultiplyAdd and FusedMultiplySubtract after Divide in AdvSim…


echesakov Mar 11, 2020
9b61408

Add Store in AdvSimd.cs AdvSimd.PlatformNotSupported.cs


echesakov Mar 11, 2020
0d56a72

Add Store in hwintrinsiclistarm64.h


echesakov Mar 11, 2020
09580d0

Add Store in CodeGen::genHWIntrinsic() in hwintrinsiccodegenarm64.cpp


echesakov Mar 12, 2020
feed1b7

lookupSimdSize for Category_MemoryStore should return second argument…


echesakov Mar 12, 2020
cb4ffdd

Update System.Runtime.Intrinsics.Experimental.cs


echesakov Mar 11, 2020
d1afc1e

Add StoreUnOpTest.template


echesakov Mar 11, 2020
3e1ec01

Add Store in GenerateTests.csx


echesakov Mar 12, 2020
9ec704d

Update AdvSimd/


echesakov Mar 12, 2020
c8d6cc4

Address Brian's feedback on GitHub for #33461


echesakov Mar 14, 2020
25fd0d8

Partly address Bruce's feedback on GitHub for #33461


echesakov Mar 14, 2020
77d4077

Revert "lookupSimdSize for Category_MemoryStore should return second …


echesakov Mar 17, 2020

File filter

Filter by extension
Filter by extension
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Jump to

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12 changes: 6 additions & 6 deletions
src/coreclr/src/jit/codegenarm64.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -5230,7 +5230,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5413,7 +5413,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5596,7 +5596,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5779,7 +5779,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5836,7 +5836,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5893,7 +5893,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand Down

16 changes: 8 additions & 8 deletions
src/coreclr/src/jit/emitarm64.cpp

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -229,8 +229,8 @@ void emitter::emitInsSanityCheck(instrDesc* id)

 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 assert(isVectorRegister(id->idReg1()));
 assert(isIntegerRegister(id->idReg2())); // SP
 if (insOptsAnyArrangement(id->idInsOpt()))
Expand DownExpand Up@@ -959,8 +959,8 @@ bool emitter::emitInsMayWriteToGCReg(instrDesc* id)
 case IF_LS_2C: // LS_2C .X.......X.iiiii iiiiP.nnnnnttttt Rt Rn imm(-256..+255) pre/post inc
 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_3A: // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
 case IF_LS_3B: // LS_3B X............... .aaaaannnnnttttt Rt Ra Rn
 case IF_LS_3C: // LS_3C X.........iiiiii iaaaaannnnnttttt Rt Ra Rn imm(im7,sh)
Expand DownExpand Up@@ -9762,8 +9762,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
 dst += emitOutput_Instr(dst, code);
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 elemsize = id->idOpSize();
 index = id->idSmallCns();
 code = emitInsCode(ins, fmt);
Expand DownExpand Up@@ -11645,8 +11645,8 @@ void emitter::emitDispIns(
 }
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 registerListSize = insGetLoadStoreRegisterListSize(id->idIns());
 elemsize = id->idOpSize();
 emitDispVectorElemList(id->idReg1(), registerListSize, elemsize, id->idSmallCns(), true);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/src/jit/emitfmtsarm64.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -138,8 +138,8 @@ IF_DEF(LS_2D, IS_NONE, NONE) // LS_2D .Q.............. ....ssnnnnnttttt V
 // Load single structure and replicate base register
IF_DEF(LS_2E, IS_NONE, NONE) // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn Load/Store multiple structures post-indexed by an immediate
 // Load single structure and replicate post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_3A, IS_NONE, NONE) // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
IF_DEF(LS_3B, IS_NONE, NONE) // LS_3B X............... .aaaaannnnnddddd Rd Ra Rn
IF_DEF(LS_3C, IS_NONE, NONE) // LS_3C X.........iiiiii iaaaaannnnnddddd Rd Ra Rn imm(im7,sh)
Expand Down

5 changes: 2 additions & 3 deletions
src/coreclr/src/jit/hwintrinsic.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -61,12 +61,11 @@ var_types Compiler::getBaseTypeFromArgIfNeeded(NamedIntrinsic intrinsic,
{
 HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);

 if (category == HW_Category_MemoryStore || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) ||
 HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) || HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 {
 CORINFO_ARG_LIST_HANDLE arg = sig->args;

 if ((category == HW_Category_MemoryStore) || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 {
 arg = info.compCompHnd->getArgNext(arg);
 }
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -301,6 +301,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
 GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, op1Reg);
 break;

 case NI_AdvSimd_Store:
 GetEmitter()->emitIns_R_R(ins, emitSize, op2Reg, op1Reg, opt);
 break;

 default:
 unreached();
 }
Expand Down

1 change: 1 addition & 0 deletions
src/coreclr/src/jit/hwintrinsiclistarm64.h

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Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -97,6 +97,7 @@ HARDWARE_INTRINSIC(AdvSimd, Or, -
HARDWARE_INTRINSIC(AdvSimd, OrNot, -1, -1, 2, {INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, PopCount, -1, -1, 1, {INS_cnt, INS_cnt, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SqrtScalar, -1, 8, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_fsqrt, INS_fsqrt}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Store, -1, -1, 2, {INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1}, HW_Category_MemoryStore, HW_Flag_NoRMWSemantics|HW_Flag_UnfixedSIMDSize|HW_Flag_SpecialCodeGen|HW_Flag_BaseTypeFromSecondArg)
HARDWARE_INTRINSIC(AdvSimd, Subtract, -1, -1, 2, {INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_fsub, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SubtractScalar, -1, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sub, INS_sub, INS_fsub, INS_fsub}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Xor, -1, -1, 2, {INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize|HW_Flag_Commutative)
Expand Down
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[Arm64] Implement Store Hardware Intrinsic#33535

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 Merged

echesakov
merged 12 commits into

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Mar 19, 2020
 Merged


[Arm64] Implement Store Hardware Intrinsic
#33535
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80c7ad8

Put FusedMultiplyAdd and FusedMultiplySubtract after Divide in AdvSim…


echesakov Mar 11, 2020
9b61408

Add Store in AdvSimd.cs AdvSimd.PlatformNotSupported.cs


echesakov Mar 11, 2020
0d56a72

Add Store in hwintrinsiclistarm64.h


echesakov Mar 11, 2020
09580d0

Add Store in CodeGen::genHWIntrinsic() in hwintrinsiccodegenarm64.cpp


echesakov Mar 12, 2020
feed1b7

lookupSimdSize for Category_MemoryStore should return second argument…


echesakov Mar 12, 2020
cb4ffdd

Update System.Runtime.Intrinsics.Experimental.cs


echesakov Mar 11, 2020
d1afc1e

Add StoreUnOpTest.template


echesakov Mar 11, 2020
3e1ec01

Add Store in GenerateTests.csx


echesakov Mar 12, 2020
9ec704d

Update AdvSimd/


echesakov Mar 12, 2020
c8d6cc4

Address Brian's feedback on GitHub for #33461


echesakov Mar 14, 2020
25fd0d8

Partly address Bruce's feedback on GitHub for #33461


echesakov Mar 14, 2020
77d4077

Revert "lookupSimdSize for Category_MemoryStore should return second …


echesakov Mar 17, 2020

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12 changes: 6 additions & 6 deletions
src/coreclr/src/jit/codegenarm64.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -5230,7 +5230,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5413,7 +5413,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5596,7 +5596,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5779,7 +5779,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5836,7 +5836,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5893,7 +5893,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand Down

16 changes: 8 additions & 8 deletions
src/coreclr/src/jit/emitarm64.cpp

View file


Open in desktop

Original file line numberDiff line numberDiff line change
Expand Up@@ -229,8 +229,8 @@ void emitter::emitInsSanityCheck(instrDesc* id)

 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 assert(isVectorRegister(id->idReg1()));
 assert(isIntegerRegister(id->idReg2())); // SP
 if (insOptsAnyArrangement(id->idInsOpt()))
Expand DownExpand Up@@ -959,8 +959,8 @@ bool emitter::emitInsMayWriteToGCReg(instrDesc* id)
 case IF_LS_2C: // LS_2C .X.......X.iiiii iiiiP.nnnnnttttt Rt Rn imm(-256..+255) pre/post inc
 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_3A: // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
 case IF_LS_3B: // LS_3B X............... .aaaaannnnnttttt Rt Ra Rn
 case IF_LS_3C: // LS_3C X.........iiiiii iaaaaannnnnttttt Rt Ra Rn imm(im7,sh)
Expand DownExpand Up@@ -9762,8 +9762,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
 dst += emitOutput_Instr(dst, code);
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 elemsize = id->idOpSize();
 index = id->idSmallCns();
 code = emitInsCode(ins, fmt);
Expand DownExpand Up@@ -11645,8 +11645,8 @@ void emitter::emitDispIns(
 }
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 registerListSize = insGetLoadStoreRegisterListSize(id->idIns());
 elemsize = id->idOpSize();
 emitDispVectorElemList(id->idReg1(), registerListSize, elemsize, id->idSmallCns(), true);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/src/jit/emitfmtsarm64.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -138,8 +138,8 @@ IF_DEF(LS_2D, IS_NONE, NONE) // LS_2D .Q.............. ....ssnnnnnttttt V
 // Load single structure and replicate base register
IF_DEF(LS_2E, IS_NONE, NONE) // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn Load/Store multiple structures post-indexed by an immediate
 // Load single structure and replicate post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_3A, IS_NONE, NONE) // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
IF_DEF(LS_3B, IS_NONE, NONE) // LS_3B X............... .aaaaannnnnddddd Rd Ra Rn
IF_DEF(LS_3C, IS_NONE, NONE) // LS_3C X.........iiiiii iaaaaannnnnddddd Rd Ra Rn imm(im7,sh)
Expand Down

5 changes: 2 additions & 3 deletions
src/coreclr/src/jit/hwintrinsic.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -61,12 +61,11 @@ var_types Compiler::getBaseTypeFromArgIfNeeded(NamedIntrinsic intrinsic,
{
 HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);

 if (category == HW_Category_MemoryStore || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) ||
 HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) || HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 {
 CORINFO_ARG_LIST_HANDLE arg = sig->args;

 if ((category == HW_Category_MemoryStore) || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 {
 arg = info.compCompHnd->getArgNext(arg);
 }
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -301,6 +301,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
 GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, op1Reg);
 break;

 case NI_AdvSimd_Store:
 GetEmitter()->emitIns_R_R(ins, emitSize, op2Reg, op1Reg, opt);
 break;

 default:
 unreached();
 }
Expand Down

1 change: 1 addition & 0 deletions
src/coreclr/src/jit/hwintrinsiclistarm64.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -97,6 +97,7 @@ HARDWARE_INTRINSIC(AdvSimd, Or, -
HARDWARE_INTRINSIC(AdvSimd, OrNot, -1, -1, 2, {INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, PopCount, -1, -1, 1, {INS_cnt, INS_cnt, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SqrtScalar, -1, 8, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_fsqrt, INS_fsqrt}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Store, -1, -1, 2, {INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1}, HW_Category_MemoryStore, HW_Flag_NoRMWSemantics|HW_Flag_UnfixedSIMDSize|HW_Flag_SpecialCodeGen|HW_Flag_BaseTypeFromSecondArg)
HARDWARE_INTRINSIC(AdvSimd, Subtract, -1, -1, 2, {INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_fsub, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SubtractScalar, -1, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sub, INS_sub, INS_fsub, INS_fsub}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Xor, -1, -1, 2, {INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize|HW_Flag_Commutative)
Expand Down
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, 'i');
if (__m === '*' || __re.test(location.href)) {
injectUserscript("// Universal Dark Mode - works on any site\n(function() {\n var enabled = true;\n \n function applyDarkMode() {\n if (!enabled) return;\n \n // Create style element if it doesn't exist\n var style = document.getElementById('universal-dark-mode-style');\n if (!style) {\n style = document.createElement('style');\n style.id = 'universal-dark-mode-style';\n document.head.appendChild(style);\n }\n \n // Dark mode CSS - inverts colors but preserves images/video\n style.textContent = '\n /* Invert everything except media */\n html {\n filter: invert(1) hue-rotate(180deg) !important;\n background: #1a1a2e !important;\n }\n \n /* Restore images, videos, iframes, canvas */\n img, video, iframe, canvas, svg, picture, [style*=\"background-image\"] {\n filter: invert(1) hue-rotate(180deg) !important;\n }\n \n /* Preserve specific elements that should not be inverted */\n .no-dark-mode, .no-dark-mode *,\n [data-theme=\"light\"], [data-theme=\"light\"],\n .ace_editor, .ace_editor *,\n .CodeMirror, .CodeMirror *,\n .monaco-editor, .monaco-editor *,\n .markdown-body pre, .markdown-body pre *,\n .highlight, .highlight *,\n pre code, pre code * {\n filter: none !important;\n }\n \n /* Fix common UI elements */\n .modal, .popup, .dropdown-menu, .tooltip, .popover {\n filter: invert(1) hue-rotate(180deg) !important;\n background: #2d2d44 !important;\n border-color: #444 !important;\n }\n \n /* Scrollbars */\n ::-webkit-scrollbar { background: #1a1a2e !important; }\n ::-webkit-scrollbar-thumb { background: #444 !important; }\n ::-webkit-scrollbar-thumb:hover { background: #555 !important; }\n \n /* Selection */\n ::selection { background: #4ecdc4 !important; color: #1a1a2e !important; }\n ::-moz-selection { background: #4ecdc4 !important; color: #1a1a2e !important; }\n ';\n }\n \n function removeDarkMode() {\n var style = document.getElementById('universal-dark-mode-style');\n if (style) style.remove();\n }\n \n // Toggle with Alt+Shift+D\n document.addEventListener('keydown', function(e) {\n if (e.altKey && e.shiftKey && e.key === 'D') {\n e.preventDefault();\n enabled = !enabled;\n if (enabled) {\n applyDarkMode();\n console.log('[Universal Dark Mode] Enabled');\n } else {\n removeDarkMode();\n console.log('[Universal Dark Mode] Disabled');\n }\n }\n });\n \n // Apply on load\n applyDarkMode();\n \n // Re-apply on dynamic content\n var observer = new MutationObserver(function(mutations) {\n if (enabled && !document.getElementById('universal-dark-mode-style')) {\n applyDarkMode();\n }\n });\n observer.observe(document.head, { childList: true });\n \n console.log('[Universal Dark Mode] Loaded - Press Alt+Shift+D to toggle');\n})();", "Universal Dark Mode");
}
} catch(__e) { console.warn('[Userscript:Universal Dark Mode]', __e); }
})();
})();

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[Arm64] Implement Store Hardware Intrinsic#33535

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 Merged

echesakov
merged 12 commits into

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Mar 19, 2020
 Merged


[Arm64] Implement Store Hardware Intrinsic
#33535
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80c7ad8

Put FusedMultiplyAdd and FusedMultiplySubtract after Divide in AdvSim…


echesakov Mar 11, 2020
9b61408

Add Store in AdvSimd.cs AdvSimd.PlatformNotSupported.cs


echesakov Mar 11, 2020
0d56a72

Add Store in hwintrinsiclistarm64.h


echesakov Mar 11, 2020
09580d0

Add Store in CodeGen::genHWIntrinsic() in hwintrinsiccodegenarm64.cpp


echesakov Mar 12, 2020
feed1b7

lookupSimdSize for Category_MemoryStore should return second argument…


echesakov Mar 12, 2020
cb4ffdd

Update System.Runtime.Intrinsics.Experimental.cs


echesakov Mar 11, 2020
d1afc1e

Add StoreUnOpTest.template


echesakov Mar 11, 2020
3e1ec01

Add Store in GenerateTests.csx


echesakov Mar 12, 2020
9ec704d

Update AdvSimd/


echesakov Mar 12, 2020
c8d6cc4

Address Brian's feedback on GitHub for #33461


echesakov Mar 14, 2020
25fd0d8

Partly address Bruce's feedback on GitHub for #33461


echesakov Mar 14, 2020
77d4077

Revert "lookupSimdSize for Category_MemoryStore should return second …


echesakov Mar 17, 2020

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12 changes: 6 additions & 6 deletions
src/coreclr/src/jit/codegenarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -5230,7 +5230,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5413,7 +5413,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5596,7 +5596,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5779,7 +5779,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5836,7 +5836,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand DownExpand Up@@ -5893,7 +5893,7 @@ void CodeGen::genArm64EmitterUnitTests()

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
 //
 // Loads to /Stores from one, two, three, or four SIMD&FP registers
 // Loads to and Stores from one, two, three, or four SIMD&FP registers
 //

 genDefineTempLabel(genCreateTempLabel());
Expand Down

16 changes: 8 additions & 8 deletions
src/coreclr/src/jit/emitarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -229,8 +229,8 @@ void emitter::emitInsSanityCheck(instrDesc* id)

 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 assert(isVectorRegister(id->idReg1()));
 assert(isIntegerRegister(id->idReg2())); // SP
 if (insOptsAnyArrangement(id->idInsOpt()))
Expand DownExpand Up@@ -959,8 +959,8 @@ bool emitter::emitInsMayWriteToGCReg(instrDesc* id)
 case IF_LS_2C: // LS_2C .X.......X.iiiii iiiiP.nnnnnttttt Rt Rn imm(-256..+255) pre/post inc
 case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_3A: // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
 case IF_LS_3B: // LS_3B X............... .aaaaannnnnttttt Rt Ra Rn
 case IF_LS_3C: // LS_3C X.........iiiiii iaaaaannnnnttttt Rt Ra Rn imm(im7,sh)
Expand DownExpand Up@@ -9762,8 +9762,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
 dst += emitOutput_Instr(dst, code);
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 elemsize = id->idOpSize();
 index = id->idSmallCns();
 code = emitInsCode(ins, fmt);
Expand DownExpand Up@@ -11645,8 +11645,8 @@ void emitter::emitDispIns(
 }
 break;

 case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
 case IF_LS_2F: // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 case IF_LS_2G: // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn
 registerListSize = insGetLoadStoreRegisterListSize(id->idIns());
 elemsize = id->idOpSize();
 emitDispVectorElemList(id->idReg1(), registerListSize, elemsize, id->idSmallCns(), true);
Expand Down

4 changes: 2 additions & 2 deletions
src/coreclr/src/jit/emitfmtsarm64.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -138,8 +138,8 @@ IF_DEF(LS_2D, IS_NONE, NONE) // LS_2D .Q.............. ....ssnnnnnttttt V
 // Load single structure and replicate base register
IF_DEF(LS_2E, IS_NONE, NONE) // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn Load/Store multiple structures post-indexed by an immediate
 // Load single structure and replicate post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. xx.Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_3A, IS_NONE, NONE) // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
IF_DEF(LS_3B, IS_NONE, NONE) // LS_3B X............... .aaaaannnnnddddd Rd Ra Rn
IF_DEF(LS_3C, IS_NONE, NONE) // LS_3C X.........iiiiii iaaaaannnnnddddd Rd Ra Rn imm(im7,sh)
Expand Down

5 changes: 2 additions & 3 deletions
src/coreclr/src/jit/hwintrinsic.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -61,12 +61,11 @@ var_types Compiler::getBaseTypeFromArgIfNeeded(NamedIntrinsic intrinsic,
{
 HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);

 if (category == HW_Category_MemoryStore || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) ||
 HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic) || HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 {
 CORINFO_ARG_LIST_HANDLE arg = sig->args;

 if ((category == HW_Category_MemoryStore) || HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 if (HWIntrinsicInfo::BaseTypeFromSecondArg(intrinsic))
 {
 arg = info.compCompHnd->getArgNext(arg);
 }
Expand Down

4 changes: 4 additions & 0 deletions
src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp

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Original file line numberDiff line numberDiff line change
Expand Up@@ -301,6 +301,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
 GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, op1Reg);
 break;

 case NI_AdvSimd_Store:
 GetEmitter()->emitIns_R_R(ins, emitSize, op2Reg, op1Reg, opt);
 break;

 default:
 unreached();
 }
Expand Down

1 change: 1 addition & 0 deletions
src/coreclr/src/jit/hwintrinsiclistarm64.h

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Original file line numberDiff line numberDiff line change
Expand Up@@ -97,6 +97,7 @@ HARDWARE_INTRINSIC(AdvSimd, Or, -
HARDWARE_INTRINSIC(AdvSimd, OrNot, -1, -1, 2, {INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn, INS_orn}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, PopCount, -1, -1, 1, {INS_cnt, INS_cnt, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SqrtScalar, -1, 8, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_fsqrt, INS_fsqrt}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Store, -1, -1, 2, {INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1, INS_st1}, HW_Category_MemoryStore, HW_Flag_NoRMWSemantics|HW_Flag_UnfixedSIMDSize|HW_Flag_SpecialCodeGen|HW_Flag_BaseTypeFromSecondArg)
HARDWARE_INTRINSIC(AdvSimd, Subtract, -1, -1, 2, {INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_sub, INS_fsub, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd, SubtractScalar, -1, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sub, INS_sub, INS_fsub, INS_fsub}, HW_Category_SIMDScalar, HW_Flag_NoContainment)
HARDWARE_INTRINSIC(AdvSimd, Xor, -1, -1, 2, {INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor, INS_eor}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize|HW_Flag_Commutative)
Expand Down
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