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reg_field: add field_matvec_rls/diag_rls/relax_rls device dispatch + bump pins - #39
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…bump pins Wires the reweighted-least-squares (RLS/JRLS) field regulariser API through the device-dispatch boundary: inspects the tensor's device and forwards to FF_CUDA:: (guarded by FF_WITH_CUDA) or FF_CPU::, mirroring the existing field_matvec/field_diag/field_relax dispatch. Declared in reg_field.h with the same signature as the CPU/CUDA libraries (an additional `wgt` tensor threaded alongside out/inp or sol/hes/grd). Bump submodule pins to the commits that add the RLS/JRLS dispatch on each backend: cpu -> fastfields-cpu-lib#40, cuda -> fastfields-cuda-lib#25. Same bending-order correctness caveat as the backend dispatch layers applies (tracked in fastfields-kernels#34) -- absolute/membrane are the verified-symmetric paths; documented in the field_matvec_rls docstring. Verified: `make all CXX=clang++` builds libfastfields-cpu.so and libfastfields.so clean. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_016AjQcY78NgbagPSbPJRr6Z
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Summary
Wires the reweighted-least-squares (RLS/JRLS) field regulariser API through the device-dispatch boundary: inspects the tensor's device and forwards to
FF_CUDA::(guarded byFF_WITH_CUDA) orFF_CPU::, mirroring the existingfield_matvec/field_diag/field_relaxdispatch.reg_field.hwith the same signature as the CPU/CUDA libraries (an additionalwgttensor threaded alongsideout/inporsol/hes/grd).cpu→ fastfields-cpu-lib#40,cuda→ fastfields-cuda-lib#25.This completes the field RLS/JRLS cascade through the native C++/CUDA stack (kernels → cpu-impl/cuda-impl → cpu-lib/cuda-lib → lib). Same
bending-order correctness caveat as the backend dispatch layers applies (tracked in fastfields-kernels#34) —absolute/membraneare the verified-symmetric paths; documented in thefield_matvec_rlsdocstring.Testing
make all CXX=clang++buildslibfastfields-cpu.soandlibfastfields.soclean.🤖 Generated with Claude Code
Generated by Claude Code