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OpenHW Group

README.md

About OpenHW Foundation

OpenHW Foundation (formally the OpenHW Group) is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices. Please see our website for membership information, latest news, and further resources.

Project Repositories Table of Contents

Working GroupRepoDescription
Cores TGCore-v-cores roadmap
CTG meetings and minutes
In Active DevelopmentCVA66-stage, application-class and embedded-class configurable core family
CVW5-stage, application-class core with education focus
CV32E40PV24-stage, embedded-class core extending CV32E40Pv1 with FPU and PULP extensions
CV32E40S4-stage, embedded-class core with security focus
CV32E202-stage, embedded-class microcontroller core and core complex
CV32E40PX (repo TBD)4-stage, embedded-class core extending CV32E40Pv2 with RVB/RVK/RVP and CV-X-IF
CompletedCV32E40P4-stage, embedded-class core implementing PULP extensions at TRL5
CVA55-stage, FPGA-optimized application-class core at TRL3
CV32E41P4-stage, embedded-class core prototyping Zfinx and Zce at TRL3
Inactive projectCV32E40X4-stage, embedded-class core supporting X-Interface
Verification TGVTG meetings and minutes
CORE-V VerifCommon test bench for OpenHW Cores
FORCE RISC-VAdvanced RISC-V instruction set generator
Software TGSWTG meetings and minutes
CORE-V GNU ToolsGNU Tools Project for embedded-class CORE-V cores
CORE-V LLVMLLVM Tools Project for embedded-class CORE-V cores
CORE-V FreeRTOS KernelFreeRTOS Kernel for embedded-class CORE-V cores
CORE-V FreeRTOSFreeRTOS for embedded-class CORE-V cores
CORE-V QEMUQEMU emulator for CORE-V-MCU
CORE-V SDKSDK and IDE for 4-stage CORE-V cores
CVA6 SDKSoftware tools for the CVA6 core
Interconnect TG
CV-HPDCACHEHigh performance L1 Data Cache
CV-MESH (repo TBD)Coherency framework based on Open Piton
CV-TCCCTightly-coupled cache coherence for CVA6
CORE-V VISION APU (repo TBD)Machine learning SoC including CVA6 and CV-VEC
CVA6-PlatformMulti-core CVA6 with CV-MESH intended for software testing
CORE-V-POLARA-APUMulticore CVA6/CVVEC ASIC with CV-MESH
CORE-V-POLARA-DEVKIT (repo TBD)Development board for Polara APU
Hardware TGHWTG meetings and minutes
CORE-V-MCUASIC and FPGA MCU implementation of CV32E40P
CORE-V-MCU-DEVKITDevkit for CORE-V-MCU
Technical Working GroupOpenHW project dashboard
Project Description Folders
OpenHW Project process and templates

Popular repositories Loading

  1. cva6 cva6Public

    The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

    Assembly 3.1k 999

  2. cv32e40p cv32e40pPublic

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    SystemVerilog 1.3k 546

  3. core-v-verif core-v-verifPublic

    Functional verification project for the CORE-V family of RISC-V cores.

    Assembly 710 323

  4. cvfpu cvfpuPublic

    Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

    SystemVerilog 631 170

  5. cvw cvwPublic

    CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

    SystemVerilog 600 548

  6. core-v-cores core-v-coresPublic

    CORE-V Family of RISC-V Cores

    366 27

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