6.18: Add Arduino VENTUNO Q (QCS8300) board support by ricardosalveti · Pull Request #1013 · qualcomm-linux/kernel

Ricardo Salveti (ricardosalveti) · 2026-08-25T17:00:30Z

Backport series enabling the Arduino VENTUNO Q (monaco-arduino-monza, QCS8300/Monaco)
on qcom-6.18.y. 36 commits: 14 UPSTREAM, 12 FROMGIT, 10 BACKPORT.

The BACKPORT ones are mostly context-only conflicts. The exceptions worth calling out:
the refgen commit is applied to monaco.dtsi, since upstream still calls that file
qcs8300.dtsi; the sc8280xp one keeps this branch's snd_soc_common name and its
shikra blocks, and keeps the existing unchecked snd_soc_dai_set_fmt() rather than
adding error handling that would change behaviour for every other board on that
machine driver; and two commits carry a Link: this backporter added, because the
upstream commits have none.

SoC DT + bindings (monaco.dtsi): refgen regulator, USB1 HS/SS endpoints, the
missing usb-role-switch (without it dwc3 registers no role switch for the board's
only USB-C data port), the PCIe iommu-map 5-cell fix (pcie_smmu has
#iommu-cells = <2>, and the SoM only overrides pcie0, so pcie1's map is malformed
today), the CSI I2C bus frequency fix (1 MHz → 400 kHz — not camera-only here, the
EMC2305 fan controller hangs off cci1_i2c1), and the LPASS LPI pin controller
binding + DT node.
Board: arduino vendor prefix, the arduino,monza compatible, the Monza SoM,
the board DTS, and the follow-ups upstream has since added — Bluetooth UART,
duplicate includes, the SoM PCIe iommu-map fix, USB-C controller and connector,
fan controller and thermal cooling, DisplayPort audio, and the INA232 power sensor.
INA232 hwmon (5 commits): the ina2xx refactor chain, the INA234 binding and
support it builds on, and INA232 itself. Without these the board's power monitor is
an inert DT node — the driver has no ti,ina232 entry.
Audio LPI MI2S (9 commits): the board's sound card uses q6apmbedai ports
137/138/145, which do not exist on this branch. The chain bottoms out at
ASoC: qcom: common: validate cpu dai id during parsing, which introduces the single
LPASS_MAX_PORT definition — without it the port arrays in q6afe are indexed past
their bounds and the build fails outright.
Fixes: gcc-qcs8300 PCIe GDSC retention (the PCIe link does not survive resume
without it), and the QCS8300 cpufreq-dt-platdev blocklist entry, otherwise
cpufreq-dt races the real qcom-cpufreq-hw driver.
Config: CONFIG_QCA808X_PHY for the QCA8081 ethernet PHY.

Deliberately not taken: the qcs8300.dtsi → monaco.dtsi rename (this branch already
uses the new name) and the tree-wide pci@ → pcie@ rename; the 9-commit drm/msm/dp
HPD and link-training rework; Senary MI2S support, which would register two unused DAIs
on every q6afe platform on this branch; the SDC1 pinctrl, extra fastrpc compute
contexts, default GIC address cells, PDC DRV span and CPU idle-state changes in
monaco.dtsi; minidump SRAM and TSCSS clocks; the qcs8300-pmics allow-set-time
removal, which changes RTC behaviour for every monaco board; camera pinctrl/regulator
commits; and monaco-evk / qcs8300-ride board changes.

Validation

Built with meta-qcom / meta-qcom-3rdparty and booted on real hardware in LAVA, both
core-image-base (nodistro) and qcom-multimedia-image (qcom-distro). Working: both
PCIe root ports enumerating through to the TI TUSB73x0 xHCI, ethernet with the QCA8081
PHY bound via qcom-ethqos, qcom-cpufreq-hw scaling, the INA232 power monitor,
HDMI (ADV7535) and DisplayPort connectors, Type-C with partner detection, ADSP/CDSP/GPDSP
remoteprocs with five /dev/fastrpc-* nodes, iris decode + encode, Bluetooth, 40 thermal
zones. No oops.

monaco-arduino-monza.dtb passes CHECK_DTBS=y; its only warnings are pre-existing
monaco.dtsi ones that every other monaco board already produces on this branch
(qcom,qcs8300-cci clock-names, the gp_mn TLMM state). A base-vs-head comparison
across the whole monaco family shows zero new warning kinds, and every binding this
series touches is permissive — widened enums, a const relaxed to oneOf, an extended
range — so no other platform can regress. All five touched bindings pass
dt_binding_check.

Known gaps

Audio does not come up. The card fails to register with
snd-sc8280xp: HDMI Playback: codec dai not found, and since one failing dai-link
takes down the whole card, the MAX98090 analog path is down with it. The cause is in
the upstream board DTS, not this series: the hdmi-mi2s-playback-dai-link names
&adv7535 as its codec, but the adv7511 driver advertises
hdmi_audio_dai_port = 2 and the node has only port@0/port@1 and
#sound-dai-cells = <0>. The pattern that works upstream (qrb5165-rb5 with
lt9611uxc) uses #sound-dai-cells = <1> plus a port@2. The ASoC component is
registered (hdmi-audio-codec.2.auto appears alongside max98090.2-0010); only the
DAI lookup fails. Needs an upstream DTS fix.
The EMC2305 fan controller never probes.CONFIG_SENSORS_EMC2305=y, the driver
registers and its OF table matches, and the i2c client is created from DT with the
right modalias — but it is parked with a waiting_for_supplier attribute, never
bound, and there is not a single emc2305 line in dmesg. fw_devlink is holding it.
The suspect shape is the self-referential pwms = <&fan_controller ...> in the
controller's own child combined with the thermal cooling map pointing at that child.
No WiFi. The upstream board DTS describes no WLAN device at all; Bluetooth is
present as a UART serdev child.

None of these are worked around locally — they are upstream issues and should be fixed
upstream.

Add the refgen regulator block. It should be used for DSI controllers once they are added. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250921-refgen-v1-12-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit 2c9e4d7) [rsalveti: applied to monaco.dtsi, as the rename to qcs8300.dtsi is not part of this branch; the dt-bindings/thermal/thermal.h include the upstream commit adds is already present] Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

…roller Add a port node exposing the High‑Speed and Super‑Speed endpoints, allowing the USB controller to be linked through the device‑tree graph. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260313103824.2634519-2-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit 7ceeb30) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

Add missing usb-role-switch property to usb controller node. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260313103824.2634519-3-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit 2f5a32f) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd7 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 46a7c01 ("arm64: dts: qcom: qcs8300: enable pcie0") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-15-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit 2e455d9) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

qswat-orbit-external · 2026-08-25T17:00:40Z

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qswat-orbit-external · 2026-08-25T17:01:57Z

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qswat-orbit-external · 2026-08-25T17:02:57Z

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qswat-orbit-external · 2026-08-25T17:03:56Z

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…mu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd7 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 5a67924 ("arm64: dts: qcom: monaco-evk: Add IFP Mezzanine") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-17-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit b35b585) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

…uency 1 MHz is quite fast for an I2C bus and not necessarly reliable, change this to 400 KHz which is a more reasonable default. Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260723114844.63093-1-johannes.goede@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit 1c2935b) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

…8775P and QCS8300 pinctrl Document compatible for Qualcomm SA8775P and QCS8300 SoC LPASS TLMM pin controller, fully compatible with previous SM8450 generation (same amount of pins and functions). Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org> (cherry picked from commit 1c5986e) Link: https://lore.kernel.org/r/20260209134529.725573-1-mohammad.rafi.shaik@oss.qualcomm.com [rsalveti: add the Link: trailer, which the upstream commit is missing] Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

Add LPASS LPI pinctrl node used for setting MI2S and soundwire pin configs. Co-developed-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260313103824.2634519-4-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit faf08fd) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

Add entry for Arduino SRL (https://arduino.cc) Signed-off-by: Riccardo Mereu <r.mereu@arduino.cc> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20251120155825.121483-2-r.mereu.kernel@arduino.cc Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit d16ffac) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

Document Arduino monza, VENTUNO Q codename. It combines Monaco based SoM with STMicroelectronics STM32H5 microcontroller. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Co-developed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260313103824.2634519-6-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit f2915f6) [rsalveti: keep the downstream qcom,monaco-ac-evk entry alongside it] Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

The Monaco Monza SoM is a compact computing module that integrates a Monaco/QCS8300 System on Chip (SoC), along with essential components optimized for IoT applications. It is designed to be mounted on carrier boards, enabling the development of complete embedded systems. The following components are described: - Fixed S2S 1.8V rail - PMM8654AU RPMh regulators (PMIC A and PMIC C) - Display subsystem/phy supplies (DSI, DP) - Enable GPU, GPI DMA, IRIS - PCIe Gen4 for both controllers and PHY supply hookups - QUPv3 firmware declarations - REFGEN always-on workaround for USB2 HS PHY - Remoteproc firmware names for ADSP, CDSP and GPDSP - Ethernet SERDES supplies - USB HS/SS PHY regulators - On-SoM eMMC Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Co-developed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260313103824.2634519-5-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit 5238f4e) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

Add device tree support for the Arduino VENTUNO Q board, based on the Qualcomm QCS8300 (Monaco) SoC. The board features a Qualcomm Monza SoM and integrates various peripherals, including: - USB Type‑C connector with dual‑role support - ADV7535 DSI‑to‑HDMI bridge - MAX98091 audio codec - 2.5G Ethernet PHY (HSGMII) - PCIe0 (to onboard WiFi chipset and USB bridge) - PCIe1 (to M2/nvme) - Button (via GPIO‑keys) Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Co-developed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260313103824.2634519-7-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit 70e3a61) [rsalveti: context-only Makefile conflict; mahua-crd and milos-fairphone-fp6 surround the new entry upstream but are not on this branch] Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

…node The QCA2066 Bluetooth chip is powered by a board-level 3.3 V supply provided by the hardware. This change connects the Bluetooth controller via UART10, and the corresponding GPIO is used to enable the Bluetooth chip. basic function test step: - bluetoothctl power on/off - bluetoothctl scan bredr/le - bluetoothctl pair <remote device address> - bluetoothctl connect <remote device address> low-state test and state: - rtcwake -d /dev/rtc0 -m no -s 30 && systemctl suspend cat /sys/kernel/debug/suspend_stats success: 1 fail: 0 failed_freeze: 0 failed_prepare: 0 failed_suspend: 0 failed_suspend_late: 0 failed_suspend_noirq: 0 failed_resume: 0 failed_resume_early: 0 failed_resume_noirq: 0 failures: last_failed_dev: last_failed_errno: 0 0 last_failed_step: Signed-off-by: Shuai Zhang <shuai.zhang@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260429103537.1282497-1-shuai.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit 0299c00) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

…cludes monaco-arduino-monza.dts includes monaco-monza-som.dtsi, which aleady includes monaco.dtsi and monaco-pmics.dtsi. Remove the duplicates. The resulting DTB file is identical. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260617-topic-monza_includes-v1-1-fcef9ce489fb@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit 81a1e94) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

…ntries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd7 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 5238f4e ("arm64: dts: qcom: Add Monaco Monza SoM") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-16-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit d7ae790) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

… and connector Add the Cypress USB Type-C controller and associated connector. The controller is connected over I2C12 and wired to the USB1 DWC3. The USB-C connector routes both high-speed and super-speed signals. Enable dual-role data and power over the USB-C connector. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260421101606.411335-1-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit f470169) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

…nd thermal cooling Enable the CCI1 bus and add support for the Microchip EMC2305 fan controller on the Monaco Arduino Monza board. The controller is virtually implemented by the onboard MCU. Add a new active trip point to the cpuss0 thermal zone and associate it with onboard fan cooling. The CPU subsystem sensor is used as the thermal reference until support for a more appropriate onboard/skin sensor becomes available (via spmi-adc5-gen3). Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260609091206.522331-1-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit 07d7660) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

Add support for Display port Audio on Arduino VENTUNO-Q board. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> CC: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260522100026.94760-1-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit f9665fc) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

The INA232 is a current/power monitor from Texas Instruments sharing the same register map as the other INA2xx. Signed-off-by: Martino Facchin <m.facchin@arduino.cc> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260611-monza-ina232-v2-1-e4375ce652d0@oss.qualcomm.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> (cherry picked from commit 6fe4043) [rsalveti: context-only conflict; this branch's compatible lists differ from upstream, the ti,ina232 entries added are unchanged] Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

The Arduino Monza board has a TI INA232 current/power monitor connected on I2C12 at address 0x40. It is used to measure the board supply current through a 2 milliohms shunt resistor. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260611-monza-ina232-v2-3-e4375ce652d0@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit f2a11bf) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

* Make sysfs entries documentation easier to maintain. * Use multi-line enum. * Correct "has_power_average" comment. Create a new "has_update_interval" member for chips which support averaging. Signed-off-by: Ian Ray <ian.ray@gehealthcare.com> Reviewed-by: Bence Csókás <bence98@sch.bme.hu> # v2 Tested-by: Jens Almer <bagawk@gmail.com> Link: https://lore.kernel.org/r/20260220112024.97446-3-ian.ray@gehealthcare.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> (cherry picked from commit f6e14b5) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

Add a compatible string for the INA234 device, which is like INA226 but has different scaling. Note that the device tree compatible must be different since the driver uses the compatible to configure the scaling. Signed-off-by: Ian Ray <ian.ray@gehealthcare.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> # v1 Tested-by: Jens Almer <bagawk@gmail.com> Link: https://lore.kernel.org/r/20260220112024.97446-2-ian.ray@gehealthcare.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> (cherry picked from commit ddc3dea) [rsalveti: context-only conflict; ti,ina232 was added to the same enums earlier in this series] Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

INA234 is register compatible to INA226 (excepting manufacturer and die or device id registers) but has different scaling. Signed-off-by: Ian Ray <ian.ray@gehealthcare.com> Reviewed-by: Bence Csókás <bence98@sch.bme.hu> # v2 Tested-by: Jens Almer <bagawk@gmail.com> Tested-by: Jonas Rebmann <jre@pengutronix.de> Link: https://lore.kernel.org/r/20260220112024.97446-4-ian.ray@gehealthcare.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> (cherry picked from commit 88a928e) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

The INA219 has the lowest three bits of the bus voltage register zero-reserved, the bus_voltage_shift ina2xx_config field was introduced to accommodate for that. The INA234 has four bits of the bus voltage, of the shunt voltage, and of the current registers zero-reserved but the latter two were implemented by choosing a 16x higher shunt_div instead of a separate field specifying a bit shift. This is possible because shunt voltage and current are divided by shunt_div, hence a 16x higher shunt_div results in a 16x smaller LSB for both the shunt voltage and the current register, perfectly accounting for the missing bit shift. For consistency and correctness, account for the reserved bits via shunt_voltage_shift and current_shift configuration fields as already done for voltage registers and use the conversion constants given in the INA234 datasheet. Signed-off-by: Jonas Rebmann <jre@pengutronix.de> Link: https://lore.kernel.org/r/20260303-ina234-shift-v1-2-318c33ac4480@pengutronix.de Signed-off-by: Guenter Roeck <linux@roeck-us.net> (cherry picked from commit eeca111) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

The INA232 is a current/power monitor. It shares the same register layout as the other chips in the series and uses the INA226 default configuration, but differs in its electrical characteristics: Signed-off-by: Martino Facchin <m.facchin@arduino.cc> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260611-monza-ina232-v2-2-e4375ce652d0@oss.qualcomm.com [groeck: Rephrased commit message] Signed-off-by: Guenter Roeck <linux@roeck-us.net> (cherry picked from commit d1db9b0) [rsalveti: keep the positional i2c_device_id initialisers this branch uses; the conversion to designated initialisers is not part of this series] Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

Add new dai ids entries for LPASS LPI MI2S and SENARY MI2S audio lines. Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260402081118.348071-7-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org> (cherry picked from commit e46957f) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

lpass ports numbers have been added but the afe/apm driver never got updated with new max port value that it uses to store dai specific data. There are more than one places these values are cached and always become out of sync. This will result in array out of bounds and weird driver behaviour. To catch such issues, first add a single place where we can define max port and second add a check in common parsing code which can error out before corrupting the memory with out of bounds array access. This should help both avoid and catch these type of mistakes in future. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260402081118.348071-8-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org> (cherry picked from commit d49ee8f) [rsalveti: keep the local qcom_snd_tdm_slot_cfg definition in common.h] Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

…I2S dais Add support for LPASS LPI MI2S dais in the dai-driver, these dais are used in Monaco based platform devices. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260402081118.348071-9-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org> (cherry picked from commit bcd0df1) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

…ts 5-6 There are 7 internal MI2S ports per direction found on devices with the internal sound card for Snapdragon 660. This is similar to the LPI MI2S ports, and the LPI MI2S bindings can be reused for internal MI2S. Extend the bindings for LPI MI2S ports to accommodate the internal MI2S ports. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260730174353.108023-3-mailingradian@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org> (cherry picked from commit 96591d7) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

…ts 5-6 Add the extra LPI MI2S ports used for internal MI2S on SDM660. Link: https://android.googlesource.com/kernel/msm-extra/+/530cffa4cc977a348753831b163eb9d3302b954a/asoc/msm-dai-q6-v2.c#4597 Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260730174353.108023-7-mailingradian@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org> (cherry picked from commit 6840019) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

The bindings for LPI MI2S ports, originally exclusive to q6apm, can be used for internal MI2S ports on q6afe. Add the port mappings for internal MI2S, found on the Snapdragon 660 internal sound card. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260730174353.108023-8-mailingradian@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org> (cherry picked from commit bfe9098) [rsalveti: context-only conflicts around the AFE port id defines and the port switch; the added lines themselves are unchanged] Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

The bindings for LPI MI2S ports, originally exclusive to q6apm, can be used for internal MI2S ports on q6afe. Add the internal MI2S ports found on the SDM660 internal sound card using the LPI MI2S bindings. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260730174353.108023-9-mailingradian@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org> (cherry picked from commit 0b494ae) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

Add the ASM-AFE routing for LPI MI2S ports which represent internal MI2S ports on SDM660. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260730174353.108023-10-mailingradian@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org> (cherry picked from commit 14d3cca) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

Update dai-ids and add DAPM widgets, sysclk and controls required for the VENTUNO-Q platform which uses MAX98090 codec. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260731162626.1588561-5-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org> (cherry picked from commit 4ba2678) [rsalveti: keep this branch's struct snd_soc_common name and its shikra widget/control blocks, and keep the existing unchecked snd_soc_dai_set_fmt() call rather than adding error handling that would change behaviour for every other board using this machine driver] Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

As the PCIe host controller driver does not yet support dealing with the loss of state during suspend, use retention for relevant GDSCs. Fix the PCIe link not surviving upon resume, and GDSC error: gcc_pcie_0_gdsc status stuck at 'off' Fixes: 95eeb2f ("clk: qcom: Add support for Global Clock Controller on QCS8300") Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260629-monza-suspend-v1-1-b601d8a2f2f8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit 11b170a) Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

The Qualcomm QCS8300 platform uses the qcom-cpufreq-hw driver, so add it to the cpufreq-dt-platdev driver's blocklist. Signed-off-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com> Reviewed-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> (cherry picked from commit d6f8e0e) Link: https://lore.kernel.org/r/20260316103752.289324-1-faruque.ansari@oss.qualcomm.com [rsalveti: add the Link: trailer, which the upstream commit is missing] Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

Enable ETHERNET PHY and Analog codec configs required for Arduino VENTUNO Q board. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260313103824.2634519-8-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> (cherry picked from commit 56f8092) [rsalveti: add CONFIG_QCA808X_PHY only; CONFIG_SND_SOC_MAX98090=m is already enabled on this branch] Signed-off-by: Ricardo Salveti <ricardo.salveti@oss.qualcomm.com>

qswat-orbit-external · 2026-08-25T21:37:10Z

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Dmitry Baryshkov (lumag)and others added 4 commits August 25, 2026 01:12

qcomlnxci requested review from a team, jingyiwang42, Dmitry Baryshkov (lumag) and Shivendra Pratap (quicAspratap)August 25, 2026 17:02

Ricardo Salveti (ricardosalveti) mentioned this pull request Aug 25, 2026
skills/qcom-kernel-platform-backport: add LTS platform backport skill qualcomm-linux/qcom-linux-skills#26
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Manivannan Sadhasivam (Mani-Sadhasivam)and others added 17 commits August 25, 2026 21:26

iangehcand others added 16 commits August 25, 2026 21:26

Ricardo Salveti (ricardosalveti)force-pushed the ventuno-q-6.18 branch from 2aa535b to 9d66e2eCompare August 25, 2026 21:37

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6.18: Add Arduino VENTUNO Q (QCS8300) board support - #1013

6.18: Add Arduino VENTUNO Q (QCS8300) board support#1013
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