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Nord PCIe changes - #914
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Shiraz Hashim (shashim-quic) merged 10 commits intoAug 24, 2026
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dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY
for all upstream/already-submitted changes can you please add Link: tag.
(so we have trackability)
Komal Bajaj (Komal-Bajaj)
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Aug 12, 2026
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why do we really need below changes for nord? dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY |
krishnachaitanya-linuxforce-pushed
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Aug 13, 2026
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Updated now, |
krishnachaitanya-linux
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Aug 13, 2026
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Removed them now. |
apateriy-qcom
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Aug 21, 2026
please rebase this PR on latest kernel tip and resolve conflicts. |
Some QMP PCIe PHY hardware blocks support multiple link topologies (e.g. x8 or x4+x4) selected via a TCSR register. The existing single-instance QMP PCIe PHY driver has no way to model this: it assumes a single cfg per DT node and instantiates exactly one PHY. Add a dedicated driver for this class of PHY. Match data carries a per-mode cfg table; qmp_pcie_multiphy_probe() reads the current link mode from the TCSR register pointed to by "qcom,link-mode", looks up the corresponding cfg array, and instantiates one qmp_pcie per sub-PHY required by that link mode, registering the clock and #phy-cells = <1> phy providers so consumers can address individual sub-PHYs by index. The driver inherits the phy setting and link-mode programmed by firmware, so only the no_csr reset is used and no phy setting tables are provided. Add the first match data and compatible, qcom,glymur-qmp-gen5x8-pcie-phy, for the Glymur Gen5 PCIe PHY that can bifurcate into two x4 links or operate as a single x8 link. Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://patch.msgid.link/20260807-glymur_linkmode_0807-v9-2-dd1c7e236e29@oss.qualcomm.com
Document the PCIe PHY found on the Qualcomm Nord platform. Nord has a Gen5-capable QMP PCIe PHY that can operate in multiple lane configurations using four PHY segments (A/B/C/D). The active topology is selected by firmware through a TCSR configuration register and may be configured as x16, x8+x8, x8+x4+x4, or x8+x4+x2+x2. The binding describes the register regions, clocks, resets, power domains, regulators, PHY provider interface, clock provider interface, and the qcom,link-mode property used by the driver to discover the active lane configuration programmed by firmware. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Add the qcom,pcie-nord compatible string to the Qualcomm PCIe controller binding. The Nord PCIe controller is compatible with the SA8775P PCIe controller implementation and reuses the same binding definition. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
…ink-mode macros Add the generic QMP_PHY_SELECTOR_* constants used to select a logical PHY instance out of a multi-PHY provider, and the Nord-specific QMP_PCIE_NORD_MODE_* constants describing the TCSR_PCIE_LINK_CONFIG_MODE encoding read by the Nord QMP PCIe multi-PHY driver. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Nord requires a workaround to address a timing convergence issue in the PCIe power domain. To avoid the issue, set the CORE_CLK_CGC_DIS and AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization. The SLV_ACLK_CGC_DIS bit is already configured by hardware reset. This change adds the remaining required settings as documented in QCTDD11972446. Introduce a dedicated Nord controller configuration and enable the workaround for qcom,pcie-nord instances. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Configure the force_mem_core and force_periph_on bits for all PCIe pipe clocks on Nord. Without these settings, PCIe data transfers are not functional and endpoints are unable to reliably access host memory through DMA. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Add support for the Nord Gen5x16 bifurcated QMP PCIe PHY. Nord has a single PCIe PHY block split into four ports which can be used in multiple lane configurations: x16, x8+x8, x8+x4+x4 and x8+x4+x2+x2. The active topology is selected through the link mode configuration register, and the driver exposes the corresponding PHY instances based on that mode. Unlike Glymur, where the PHY is initialized by firmware, Nord requires Linux to program the PHY registers. Add the PLL, TXRXZ, PCS and PCS lane initialization tables, along with the required power-up, power-down and soft-reset sequencing. Add per-port and grouped PHY configurations for all supported Nord lane modes. Also add support for regular PHY resets in addition to the NOCSR resets, and handle the shared PHY power domain by attaching it once at the multi-PHY level and reusing it across segment groups. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Nord supports four PCIe instances sharing a bifurcated PCIe PHY. The controllers support x8, x4, x2 and x2 lane configurations and are backed by a common PCIe SMMU. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Enable all four PCIe controllers (pcie0-pcie3) and the PCIe PHY on the Nord RRD (Reference Reference Design) board. Configure PHY power supplies for all four segments (A/B/C/D) and set reset GPIO pins for each PCIe root port. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Enable CONFIG_PHY_QCOM_QMP_PCIE_MULTIPHY as a module to support the shared PCIe3 PHY used by PCIe3a and PCIe3b on the Qualcomm Glymur SoC. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://patch.msgid.link/20260813-enable_multiphy_0807-v2-1-ec2a63f87874@oss.qualcomm.com
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Shiraz Hashim (shashim-quic)
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