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hda: hw support for hda chain - #6656
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4b4efffComparelgirdwood
commented
Nov 30, 2022
@makarukp is this PR still pending validation or implementation completion or external dependencies ? |
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makarukp
commented
Dec 1, 2022
@lgirdwood This PR is still under development, it requires at lease one more commit with code completion before it is ready for validation. |
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b508b85Comparemakarukp
commented
Dec 15, 2022
Code is completed. PR is ready for validation. |
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yeah, this looks a bit suspicious. And in fact dw_dma_get_status() can return -EINVAL if the channel number is invalid, and that is a hard error and in that case stat isn't filled. So, this at least deserves a comment, much more so than the two comments above which explain something, that's pretty clear from the code itself.
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@lyakh What do you think about such approach of critical error handling in response to 'dma_get_status()' ? |
lyakh
commented
Jan 16, 2023
According to https://www.alsa-project.org/alsa-doc/alsa-lib/pcm.html |
makarukp
commented
Jan 16, 2023
@lyakh Accually -EINVAL can be returned in current implementation only by dw_dma_get_status() which is used by GPDMA in Zephyr. DMA uses intel_adsp_hda_dma_status() and there is only assertion |
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kv2019i
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This starts to look good. A few minor issues, but no showstoppers.
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ipc4_chain_manager_create() seems to be a better name for this, but it's already there
Hardware HDA chain require manager for controlling multiple streams tasks. Enable support with LL task and DMA mandatory logic. Signed-off-by: Piotr Makaruk <piotr.makaruk@intel.com>
HW chain dma support require new logic in handler Signed-off-by: Piotr Makaruk <piotr.makaruk@intel.com>
Enable building chain dma component on TGL platform Signed-off-by: Piotr Makaruk <piotr.makaruk@intel.com>
Enable building chain dma component on MTL platform Signed-off-by: Piotr Makaruk <piotr.makaruk@intel.com>
Enable building chain dma component on TGL-H platform Signed-off-by: Piotr Makaruk <piotr.makaruk@intel.com>
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@lyakh this looks resolved now, error code is checked ?
marc-hb
commented
Jan 20, 2023
This apparently caused regressions #6975 and #6976. It was also merged while failing a large number of tests: https://sof-ci.01.org/sofpr/PR6656/build3409/devicetest/index.html |
lgirdwood
commented
Jan 20, 2023
There is a lot of test failures on ADL capture, I've created a revert PR that can be merged today prior to daily test runs if we don't have fixes ready in time. |
mwasko
commented
Jan 20, 2023
@lgirdwood, @kv2019i the regression is affecting only cAVS targets which are not POR in Zephyr configuration. The tests were passing before on cAVS because they were using w/a in form of copier-copier solution which is not correct implementation. We should treat it as we have enabled feature for MTL and for cAVS it is a to do action (on best effort basis). |
lgirdwood
commented
Jan 20, 2023
I'm fine to make this a MTL only feature, but it should not break legacy features on other platforms. Can this be fixed with a Kconfig ? |
@lgirdwood Unfortunately it is not possible to fix it with Kconfig because legacy approach was erased by hw chain dma PR. As for #6975 (comment) issue it does not look like a big deal. I will prepare debug FW which could probably solve that problem or provide at least more information. As for #6976 (comment) issue I don't know what happened and still thinking about further steps for debug ... |
This PR enables hardware support for HDA chain transfers (without deploying internal pipelines):
Content:
Signed-off-by: Piotr Makaruk piotr.makaruk@intel.com