chiplet

Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators

SV/DPI library allowing multiple simulations/platforms to run in parallel and communicate

Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-based Accelerators

Easy-to-use characterization framework for 2.5D chiplet links

UniCNet is a cycle-accurate simulator supporting effienct simulation for composable chiplet networks.

Risc-V Chiplet Optimization

True 3D Global Placement GUI Viewer -- An interactive 3D visualization demo for 3D IC placement. Built for the era of Huawei's Tao (τ) Law and Logic Folding, where 3D placement becomes the key enabler for next-generation chip density beyond Moore's Law.

ОТКРЫТЫЙ КОНЦЕПТ x128/x512 Микроэлектроника зашла в тупик нанометров . Концепт решает проблему расширением регистров и сокращением тактов. Вместо 4–8 шагов x64, логика x128/x512 обрабатывает массивы (ИИ, криптография) за 1–2 такта. Реализация: чиплеты через UCIe и софтверный JIT для совместимости с x86. Безвозмездно передаю идею человечеству.

Thermal-aware ChipletPart: cost, technology, floorplan, and predicted-temperature co-optimization for 2.5D chiplets.

Hard Constraint Projection enhanced neural operator with hybrid sampling for chiplet thermal analysis (Microelectronics Reliability 2026)

Physics-informed thermal surrogate benchmark for 3D/2.5D IC packaging — PINN, FNO/WHNO, PI-DeepONet, and autoregressive operators trained on real 3D-ICE ground truth across 8 geometries (single-die, TSV stacks, chiplets, CoWoS+HBM).

DeepOHeat with legacy and package-level thermal surrogate adapters for Thermal-ChipletPart.

Thermal-aware cost and technology co-optimization for early 2.5D chiplet partitioning with DeepOHeat.