ASIC implementation flow infrastructure, successor to OpenLane
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Updated
Aug 28, 2026 - Python
ASIC implementation flow infrastructure, successor to OpenLane
Agentic, evidence-driven Spec-to-RTL-to-GDS workflow with verified RTL and managed LibreLane implementation
AI/LLM-assisted circuit design using opensource tools
Chipathon 2026 workshop padring fork of wafer-space/gf180mcu-project-template - adds a workshop slot mirroring JuanMoya/padring_gf180 as a native LibreLane slot.
Browser cockpit & IDE for the LibreLane RTL-to-GDS chip flow — run, verify, and explore silicon flows without living in a terminal.
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