Open-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM source, hierarchy, and connectivity to trace failures to root cause.
mcpstatic-analysiswaveformedartlverilogsystemveriloguvmvcdverdifsdbhardware-verificationroot-cause-analysisllm-toolsrtl-verificationchip-verificationmodel-context-protocolmcp-serverpyslangsimulation-debugging
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Updated
Aug 30, 2026 - Python