apb-protocol

Here are 10 public repositories matching this topic...

Karan-nevage / APB-Protocol-Using-Verilog

Design and verification of the Advanced Peripheral Bus (APB) protocol using Verilog. Includes Verilog modules for APB operations and a testbench for verifying functionality and compliance with protocol standards.

apb amba-apb apb-verification apb-protocol apb-using-verilog

Updated Jul 28, 2025
Verilog

osaidnur / APB-FIFO-Verification-using-UVM

Star

UVM-based verification environment for an APB FIFO design with comprehensive test coverage and bug analysis.

systemverilog fifo uvm fifo-queue apb uvm-verification systemverilog-test-bench uvm-testbench apb-protocol

Updated Jun 13, 2026
SystemVerilog

harishchittaragi / DVFT11

Star

Hands-on Design Verification — SystemVerilog testbenches, full UVM environment for APB Protocol, Python scripting, SVA assertions & functional coverage. Trained at ChipEdge using Synopsys VCS.

python-script verilog synopsis systemverilog sva design-verification functional-coverage uvm-testbench apb-protocol

Updated Jul 23, 2026
SystemVerilog

Preven-K / Vending-Machine

Star

Verilog-based vending machine controller IP core, supporting multi-clock domain operation, inventory management, and currency denominations. Built with the APB protocol for efficient configuration, it offers smart change calculation and robust error handling. Developed in the SURE ProEd internship training with experts.

embedded-systems error-handling verilog memory-management vlsi digital-systems fpga-development vlsi-design hardware-design internship-project apb-protocol sure-trust vending-machine-controller sure-proed multi-clock-domain

Updated Apr 25, 2025
Verilog

dangvu2408 / apb_uart-verify

Star

Build environment for APB-UART module

asic uart systemverilog uvm-verification apb-protocol

Updated Jan 26, 2026
SystemVerilog

utkarshad21 / Verilog-HDL-Codes

Star

This repository contains Verilog codes of sequential and combinational circuits along with some protocols.

counter fsm fpga vlsi verilog-hdl shift-register digital-design combinational-logic sequential-logic clock-divider rtl-design bus-system apb-protocol

Updated Mar 17, 2026
Verilog

spunkycurative / APB-Slave-Verification-SystemVerilog

Star

Class-based SystemVerilog verification environment for an APB slave, featuring constrained-random testing, mailbox-based communication, scoreboard checking, and SystemVerilog Assertions (SVA).

verilog systemverilog vlsi digital-design sva apb design-verification constrained-random-verification rtl-design apb-protocol