A synthesizable UART design with an AMBA APB3 slave interface. Verified using SystemVerilog, Assertions (SVA), and functional coverage.
coverageassertionsuartsystemverilogsvaapbfunctional-verificationamba-apbfunctional-coveragesystemverilog-assertionsapb-protocoluart-apb-interfacing
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Updated
Jun 20, 2026 - SystemVerilog