rtl-verification

Here are 3 public repositories matching this topic...

Tencent / wave-mcp

Open-source, license-free MCP server for RTL waveform debug: reads FST waveforms (VCD/FSDB auto-convert) plus a SystemVerilog netlist, with 34 tools covering driver analysis, value/X tracing, pass-fail waveform diff, a browser wave viewer the agent drives, and pre-simulation static analysis.

mcp static-analysis waveform eda rtl debug verilog systemverilog vcd fst fsdb hardware-verification llm-tools rtl-verification chip-verification mcp-server pyslang pylibfst

Updated Sep 7, 2026
Python

gokeshenzhen / TraceWeave

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Open-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM source, hierarchy, and connectivity to trace failures to root cause.

Updated Aug 30, 2026
Python

Entropify / Entropic_R32-P5_RISC-V

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5-Stage Pipelined RISC-V CPU utilizing the RV32I ISA, featuring dynamic branch prediction. Designed, verified, performance tested, and ASIC-flowed

Updated Sep 4, 2026
Python

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