ASoC: SOF: Intel: hda: add PM state to dsp init error log by juimonen · Pull Request #2347 · thesofproject/linux

juimonen · 2020-08-06T12:17:33Z

Add PM state to dsp initialization error logging as it might give
more info what is going wrong.

Signed-off-by: Jaska Uimonen jaska.uimonen@linux.intel.com

Add PM state to dsp initialization error logging as it might give more info what is going wrong. Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>

plbossart · 2020-08-06T15:01:54Z

 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
 i, ret);
- dev_err(sdev->dev, "ROM error=0x%x: FW status=0x%x\n",
+ dev_err(sdev->dev, "ROM error=0x%x: FW status=0x%x: PM status=0x%x\n",


PM Status could be interpreted as device pm_runtime status, maybe make it clear that it's 'D0I3C status'
Also wondering how this was tested, because we don't support S0ix on any CI targets so far?

@plbossart not tested in any way... relates to this: thesofproject/sof#3267
I just tried to quickly dig out some power status registers (which I guess folks in this feature we're after).
You know this area probably much better than me, if you have some suggestions what should be logged
here to get better understanding of the power state, let me know...
If I understood @lgirdwood wanted to have the power state of DSP and PCI (bus?), not the host, somehow visible.

ok, but that specific register is only to signal D0i3, which can only happen after booting the firmware and will not help for resume or boot flows from D3.
In short I don't think this helps provide the diagnosis information @lgirdwood was asking for. I also don't understand how the DSP could be in D3 here, since it was typically powered before attempting to boot firmware. @ranj063 any ideas of what we could add here that might help triangulate such errors?

@plbossart i'll need to comb through the docs to see what might be helpful here. But I agree VS_D0I3 bit is not useful during firmware boot at all.

plus @yongzhi1 who reported the issue.

@juimonen I would also expect to see any host side DSP PM register dumped here alongside the PCI PM register. This way @yongzhi1 will know for sure.

@lgirdwood @juimonen I've added #2359 based on @mmaka1 's recommendation to dump the extended ROM status

lgirdwood · 2020-08-07T13:14:19Z

 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
 i, ret);
- dev_err(sdev->dev, "ROM error=0x%x: FW status=0x%x\n",
+ dev_err(sdev->dev, "ROM error=0x%x: FW status=0x%x: PM status=0x%x\n",


@juimonen I would also expect to see any host side DSP PM register dumped here alongside the PCI PM register. This way @yongzhi1 will know for sure.

juimonen · 2020-08-13T07:08:38Z

Ok, I'll think @ranj063 #2359 will cover the power status... should I close this?

plbossart · 2020-08-13T12:27:10Z

@lyakh another one where we PASS all tests except alsa-bat on minnowboard - I suspect we have undetected underflows that are only caught with an analysis of the captured data, see https://sof-ci.01.org/linuxpr/PR2347/build4245/devicetest/

ranj063 · 2020-08-13T17:30:13Z

Ok, I'll think @ranj063 #2359 will cover the power status... should I close this?

@juimonen yes this can be closed but I think we should look into what PCI PM registers we can dump.

juimonen · 2020-08-14T04:29:29Z

closing

…format For incoming SCO connection with transparent coding format, alt setting of CVSD is getting applied instead of Transparent. Before fix: < HCI Command: Accept Synchron.. (0x01|0x0029) plen 21 thesofproject#2196 [hci0] 321.342548 Address: 1C:CC:D6:E2:EA:80 (Xiaomi Communications Co Ltd) Transmit bandwidth: 8000 Receive bandwidth: 8000 Max latency: 13 Setting: 0x0003 Input Coding: Linear Input Data Format: 1's complement Input Sample Size: 8-bit # of bits padding at MSB: 0 Air Coding Format: Transparent Data Retransmission effort: Optimize for link quality (0x02) Packet type: 0x003f HV1 may be used HV2 may be used HV3 may be used EV3 may be used EV4 may be used EV5 may be used > HCI Event: Command Status (0x0f) plen 4 thesofproject#2197 [hci0] 321.343585 Accept Synchronous Connection Request (0x01|0x0029) ncmd 1 Status: Success (0x00) > HCI Event: Synchronous Connect Comp.. (0x2c) plen 17 thesofproject#2198 [hci0] 321.351666 Status: Success (0x00) Handle: 257 Address: 1C:CC:D6:E2:EA:80 (Xiaomi Communications Co Ltd) Link type: eSCO (0x02) Transmission interval: 0x0c Retransmission window: 0x04 RX packet length: 60 TX packet length: 60 Air mode: Transparent (0x03) ........ > SCO Data RX: Handle 257 flags 0x00 dlen 48 thesofproject#2336 [hci0] 321.383655 < SCO Data TX: Handle 257 flags 0x00 dlen 60 thesofproject#2337 [hci0] 321.389558 > SCO Data RX: Handle 257 flags 0x00 dlen 48 thesofproject#2338 [hci0] 321.393615 > SCO Data RX: Handle 257 flags 0x00 dlen 48 thesofproject#2339 [hci0] 321.393618 > SCO Data RX: Handle 257 flags 0x00 dlen 48 thesofproject#2340 [hci0] 321.393618 < SCO Data TX: Handle 257 flags 0x00 dlen 60 thesofproject#2341 [hci0] 321.397070 > SCO Data RX: Handle 257 flags 0x00 dlen 48 thesofproject#2342 [hci0] 321.403622 > SCO Data RX: Handle 257 flags 0x00 dlen 48 thesofproject#2343 [hci0] 321.403625 > SCO Data RX: Handle 257 flags 0x00 dlen 48 thesofproject#2344 [hci0] 321.403625 > SCO Data RX: Handle 257 flags 0x00 dlen 48 thesofproject#2345 [hci0] 321.403625 < SCO Data TX: Handle 257 flags 0x00 dlen 60 thesofproject#2346 [hci0] 321.404569 < SCO Data TX: Handle 257 flags 0x00 dlen 60 thesofproject#2347 [hci0] 321.412091 > SCO Data RX: Handle 257 flags 0x00 dlen 48 thesofproject#2348 [hci0] 321.413626 > SCO Data RX: Handle 257 flags 0x00 dlen 48 thesofproject#2349 [hci0] 321.413630 > SCO Data RX: Handle 257 flags 0x00 dlen 48 thesofproject#2350 [hci0] 321.413630 < SCO Data TX: Handle 257 flags 0x00 dlen 60 thesofproject#2351 [hci0] 321.419674 After fix: < HCI Command: Accept Synchronou.. (0x01|0x0029) plen 21 thesofproject#309 [hci0] 49.439693 Address: 1C:CC:D6:E2:EA:80 (Xiaomi Communications Co Ltd) Transmit bandwidth: 8000 Receive bandwidth: 8000 Max latency: 13 Setting: 0x0003 Input Coding: Linear Input Data Format: 1's complement Input Sample Size: 8-bit # of bits padding at MSB: 0 Air Coding Format: Transparent Data Retransmission effort: Optimize for link quality (0x02) Packet type: 0x003f HV1 may be used HV2 may be used HV3 may be used EV3 may be used EV4 may be used EV5 may be used > HCI Event: Command Status (0x0f) plen 4 thesofproject#310 [hci0] 49.440308 Accept Synchronous Connection Request (0x01|0x0029) ncmd 1 Status: Success (0x00) > HCI Event: Synchronous Connect Complete (0x2c) plen 17 thesofproject#311 [hci0] 49.449308 Status: Success (0x00) Handle: 257 Address: 1C:CC:D6:E2:EA:80 (Xiaomi Communications Co Ltd) Link type: eSCO (0x02) Transmission interval: 0x0c Retransmission window: 0x04 RX packet length: 60 TX packet length: 60 Air mode: Transparent (0x03) < SCO Data TX: Handle 257 flags 0x00 dlen 60 thesofproject#312 [hci0] 49.450421 < SCO Data TX: Handle 257 flags 0x00 dlen 60 thesofproject#313 [hci0] 49.457927 > HCI Event: Max Slots Change (0x1b) plen 3 thesofproject#314 [hci0] 49.460345 Handle: 256 Max slots: 5 < SCO Data TX: Handle 257 flags 0x00 dlen 60 thesofproject#315 [hci0] 49.465453 > SCO Data RX: Handle 257 flags 0x00 dlen 60 thesofproject#316 [hci0] 49.470502 > SCO Data RX: Handle 257 flags 0x00 dlen 60 thesofproject#317 [hci0] 49.470519 < SCO Data TX: Handle 257 flags 0x00 dlen 60 thesofproject#318 [hci0] 49.472996 > SCO Data RX: Handle 257 flags 0x00 dlen 60 thesofproject#319 [hci0] 49.480412 < SCO Data TX: Handle 257 flags 0x00 dlen 60 thesofproject#320 [hci0] 49.480492 < SCO Data TX: Handle 257 flags 0x00 dlen 60 thesofproject#321 [hci0] 49.487989 > SCO Data RX: Handle 257 flags 0x00 dlen 60 thesofproject#322 [hci0] 49.490303 < SCO Data TX: Handle 257 flags 0x00 dlen 60 thesofproject#323 [hci0] 49.495496 > SCO Data RX: Handle 257 flags 0x00 dlen 60 thesofproject#324 [hci0] 49.500304 > SCO Data RX: Handle 257 flags 0x00 dlen 60 thesofproject#325 [hci0] 49.500311 Signed-off-by: Kiran K <kiran.k@intel.com> Signed-off-by: Lokendra Singh <lokendra.singh@intel.com> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>

ASoC: SOF: Intel: hda: add PM state to dsp init error log
2b797cf
Add PM state to dsp initialization error logging as it might give more info what is going wrong. Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>

juimonen requested review from bardliao, dbaluta, kv2019i, lgirdwood, plbossart and ranj063 as code owners August 6, 2020 12:17

juimonen mentioned this pull request Aug 6, 2020
[FEATURE] Add diagnostic dump for reset DSP failure with status = 0xffffffff thesofproject/sof#3267
Closed

paulstelian97 approved these changes Aug 6, 2020
View reviewed changes

plbossart requested changes Aug 6, 2020
View reviewed changes

lgirdwood requested changes Aug 7, 2020
View reviewed changes

juimonen closed this Aug 14, 2020

Navigation Menu

Uh oh!

ASoC: SOF: Intel: hda: add PM state to dsp init error log - #2347

ASoC: SOF: Intel: hda: add PM state to dsp init error log#2347
juimonen wants to merge 1 commit into
thesofproject:topic/sof-devfrom
juimonen:pm_log

juimonen commented Aug 6, 2020

Uh oh!

plbossartAug 6, 2020

Uh oh!

juimonenAug 6, 2020

Uh oh!

plbossartAug 6, 2020

Uh oh!

ranj063Aug 6, 2020

Uh oh!

lgirdwoodAug 7, 2020•
edited
Loading

Uh oh!

lgirdwoodAug 7, 2020

Uh oh!

ranj063Aug 12, 2020

Uh oh!

lgirdwoodAug 7, 2020

Uh oh!

juimonen commented Aug 13, 2020

Uh oh!

plbossart commented Aug 13, 2020

Uh oh!

ranj063 commented Aug 13, 2020

Uh oh!

juimonen commented Aug 14, 2020

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

5 participants

Uh oh!

Conversation

juimonen commented Aug 6, 2020

Uh oh!

plbossartAug 6, 2020

Choose a reason for hiding this comment

Uh oh!

juimonenAug 6, 2020

Choose a reason for hiding this comment

Uh oh!

plbossartAug 6, 2020

Choose a reason for hiding this comment

Uh oh!

ranj063Aug 6, 2020

Choose a reason for hiding this comment

Uh oh!

lgirdwoodAug 7, 2020• edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

lgirdwoodAug 7, 2020

Choose a reason for hiding this comment

Uh oh!

ranj063Aug 12, 2020

Choose a reason for hiding this comment

Uh oh!

lgirdwoodAug 7, 2020

Choose a reason for hiding this comment

Uh oh!

juimonen commented Aug 13, 2020

Uh oh!

plbossart commented Aug 13, 2020

Uh oh!

ranj063 commented Aug 13, 2020

Uh oh!

juimonen commented Aug 14, 2020

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

5 participants

lgirdwoodAug 7, 2020•
edited
Loading